Lines Matching refs:dev
21 mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) in mt76x0_rf_csr_wr() argument
26 if (test_bit(MT76_REMOVED, &dev->mphy.state)) in mt76x0_rf_csr_wr()
35 mutex_lock(&dev->phy_mutex); in mt76x0_rf_csr_wr()
37 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { in mt76x0_rf_csr_wr()
42 mt76_wr(dev, MT_RF_CSR_CFG, in mt76x0_rf_csr_wr()
50 mutex_unlock(&dev->phy_mutex); in mt76x0_rf_csr_wr()
53 dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n", in mt76x0_rf_csr_wr()
59 static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset) in mt76x0_rf_csr_rr() argument
65 if (test_bit(MT76_REMOVED, &dev->mphy.state)) in mt76x0_rf_csr_rr()
74 mutex_lock(&dev->phy_mutex); in mt76x0_rf_csr_rr()
76 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) in mt76x0_rf_csr_rr()
79 mt76_wr(dev, MT_RF_CSR_CFG, in mt76x0_rf_csr_rr()
84 if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) in mt76x0_rf_csr_rr()
87 val = mt76_rr(dev, MT_RF_CSR_CFG); in mt76x0_rf_csr_rr()
93 mutex_unlock(&dev->phy_mutex); in mt76x0_rf_csr_rr()
96 dev_err(dev->mt76.dev, "Error: RF read %d:%d failed:%d!!\n", in mt76x0_rf_csr_rr()
103 mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) in mt76x0_rf_wr() argument
105 if (mt76_is_usb(&dev->mt76)) { in mt76x0_rf_wr()
112 &dev->mphy.state)); in mt76x0_rf_wr()
113 return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); in mt76x0_rf_wr()
115 return mt76x0_rf_csr_wr(dev, offset, val); in mt76x0_rf_wr()
119 static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset) in mt76x0_rf_rr() argument
124 if (mt76_is_usb(&dev->mt76)) { in mt76x0_rf_rr()
130 &dev->mphy.state)); in mt76x0_rf_rr()
131 ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); in mt76x0_rf_rr()
134 ret = val = mt76x0_rf_csr_rr(dev, offset); in mt76x0_rf_rr()
141 mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) in mt76x0_rf_rmw() argument
145 ret = mt76x0_rf_rr(dev, offset); in mt76x0_rf_rmw()
151 ret = mt76x0_rf_wr(dev, offset, val); in mt76x0_rf_rmw()
156 mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val) in mt76x0_rf_set() argument
158 return mt76x0_rf_rmw(dev, offset, 0, val); in mt76x0_rf_set()
162 mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) in mt76x0_rf_clear() argument
164 return mt76x0_rf_rmw(dev, offset, mask, 0); in mt76x0_rf_clear()
168 mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev, in mt76x0_phy_rf_csr_wr_rp() argument
173 mt76x0_rf_csr_wr(dev, data->reg, data->value); in mt76x0_phy_rf_csr_wr_rp()
178 #define RF_RANDOM_WRITE(dev, tab) do { \ argument
179 if (mt76_is_mmio(&dev->mt76)) \
180 mt76x0_phy_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
182 mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\
185 int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev) in mt76x0_phy_wait_bbp_ready() argument
191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
197 dev_err(dev->mt76.dev, "Error: BBP is not ready\n"); in mt76x0_phy_wait_bbp_ready()
201 dev_dbg(dev->mt76.dev, "BBP version %08x\n", val); in mt76x0_phy_wait_bbp_ready()
206 mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band) in mt76x0_phy_set_band() argument
210 RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab); in mt76x0_phy_set_band()
212 mt76x0_rf_wr(dev, MT_RF(5, 0), 0x45); in mt76x0_phy_set_band()
213 mt76x0_rf_wr(dev, MT_RF(6, 0), 0x44); in mt76x0_phy_set_band()
215 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007); in mt76x0_phy_set_band()
216 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002); in mt76x0_phy_set_band()
219 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); in mt76x0_phy_set_band()
221 mt76x0_rf_wr(dev, MT_RF(5, 0), 0x44); in mt76x0_phy_set_band()
222 mt76x0_rf_wr(dev, MT_RF(6, 0), 0x45); in mt76x0_phy_set_band()
224 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005); in mt76x0_phy_set_band()
225 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102); in mt76x0_phy_set_band()
233 mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, in mt76x0_phy_set_chan_rf_params() argument
260 mt76x0_rf_wr(dev, MT_RF(0, 37), freq_item->pllR37); in mt76x0_phy_set_chan_rf_params()
261 mt76x0_rf_wr(dev, MT_RF(0, 36), freq_item->pllR36); in mt76x0_phy_set_chan_rf_params()
262 mt76x0_rf_wr(dev, MT_RF(0, 35), freq_item->pllR35); in mt76x0_phy_set_chan_rf_params()
263 mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34); in mt76x0_phy_set_chan_rf_params()
264 mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33); in mt76x0_phy_set_chan_rf_params()
266 mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0, in mt76x0_phy_set_chan_rf_params()
270 mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK, in mt76x0_phy_set_chan_rf_params()
274 mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0, in mt76x0_phy_set_chan_rf_params()
278 mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK, in mt76x0_phy_set_chan_rf_params()
283 mt76x0_rf_clear(dev, MT_RF(0, 30), in mt76x0_phy_set_chan_rf_params()
285 mt76x0_rf_set(dev, MT_RF(0, 30), in mt76x0_phy_set_chan_rf_params()
288 mt76x0_rf_rmw(dev, MT_RF(0, 30), in mt76x0_phy_set_chan_rf_params()
294 mt76x0_rf_rmw(dev, MT_RF(0, 30), in mt76x0_phy_set_chan_rf_params()
299 mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK, in mt76x0_phy_set_chan_rf_params()
303 mt76x0_rf_wr(dev, MT_RF(0, 29), in mt76x0_phy_set_chan_rf_params()
306 mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1, in mt76x0_phy_set_chan_rf_params()
310 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK, in mt76x0_phy_set_chan_rf_params()
314 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK, in mt76x0_phy_set_chan_rf_params()
318 mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK, in mt76x0_phy_set_chan_rf_params()
322 mt76x0_rf_wr(dev, MT_RF(0, 26), in mt76x0_phy_set_chan_rf_params()
324 mt76x0_rf_wr(dev, MT_RF(0, 27), in mt76x0_phy_set_chan_rf_params()
327 mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3, in mt76x0_phy_set_chan_rf_params()
331 mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK, in mt76x0_phy_set_chan_rf_params()
340 mt76x0_rf_wr(dev, in mt76x0_phy_set_chan_rf_params()
345 mt76x0_rf_wr(dev, in mt76x0_phy_set_chan_rf_params()
353 mt76x0_rf_wr(dev, in mt76x0_phy_set_chan_rf_params()
359 mt76_clear(dev, MT_RF_MISC, 0xc); in mt76x0_phy_set_chan_rf_params()
362 if (mt76x02_ext_pa_enabled(dev, band)) { in mt76x0_phy_set_chan_rf_params()
370 mt76_set(dev, MT_RF_MISC, BIT(2)); in mt76x0_phy_set_chan_rf_params()
372 mt76_set(dev, MT_RF_MISC, BIT(3)); in mt76x0_phy_set_chan_rf_params()
377 mt76x0_rf_wr(dev, in mt76x0_phy_set_chan_rf_params()
383 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x63707400); in mt76x0_phy_set_chan_rf_params()
385 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); in mt76x0_phy_set_chan_rf_params()
387 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); in mt76x0_phy_set_chan_rf_params()
389 mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x686A7800); in mt76x0_phy_set_chan_rf_params()
393 mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1); in mt76x0_phy_set_chan_rf_params()
395 mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg); in mt76x0_phy_set_chan_rf_params()
400 mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band) in mt76x0_phy_set_chan_bbp_params() argument
416 gain -= dev->cal.rx.lna_gain * 2; in mt76x0_phy_set_chan_bbp_params()
419 mt76_wr(dev, pair->reg, val); in mt76x0_phy_set_chan_bbp_params()
421 mt76_wr(dev, pair->reg, pair->value); in mt76x0_phy_set_chan_bbp_params()
426 static void mt76x0_phy_ant_select(struct mt76x02_dev *dev) in mt76x0_phy_ant_select() argument
428 u16 ee_ant = mt76x02_eeprom_get(dev, MT_EE_ANTENNA); in mt76x0_phy_ant_select()
429 u16 ee_cfg1 = mt76x02_eeprom_get(dev, MT_EE_CFG1_INIT); in mt76x0_phy_ant_select()
430 u16 nic_conf2 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); in mt76x0_phy_ant_select()
434 wlan = mt76_rr(dev, MT_WLAN_FUN_CTRL); in mt76x0_phy_ant_select()
435 coex3 = mt76_rr(dev, MT_COEXCFG3); in mt76x0_phy_ant_select()
450 if (dev->mphy.cap.has_2ghz) in mt76x0_phy_ant_select()
454 if (dev->mphy.cap.has_5ghz) { in mt76x0_phy_ant_select()
462 if (is_mt7630(dev)) in mt76x0_phy_ant_select()
465 mt76_wr(dev, MT_WLAN_FUN_CTRL, wlan); in mt76x0_phy_ant_select()
466 mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant); in mt76x0_phy_ant_select()
467 mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1); in mt76x0_phy_ant_select()
468 mt76_clear(dev, MT_COEXCFG0, BIT(2)); in mt76x0_phy_ant_select()
469 mt76_wr(dev, MT_COEXCFG3, coex3); in mt76x0_phy_ant_select()
473 mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width) in mt76x0_phy_bbp_set_bw() argument
500 mt76x02_mcu_function_select(dev, BW_SETTING, bw); in mt76x0_phy_bbp_set_bw()
503 static void mt76x0_phy_tssi_dc_calibrate(struct mt76x02_dev *dev) in mt76x0_phy_tssi_dc_calibrate() argument
505 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x0_phy_tssi_dc_calibrate()
509 mt76x0_rf_clear(dev, MT_RF(0, 67), 0xf); in mt76x0_phy_tssi_dc_calibrate()
512 mt76_wr(dev, MT_RF_SETTING_0, 0x60002237); in mt76x0_phy_tssi_dc_calibrate()
513 mt76_wr(dev, MT_RF_BYPASS_0, 0xffffffff); in mt76x0_phy_tssi_dc_calibrate()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
518 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
524 mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31)); in mt76x0_phy_tssi_dc_calibrate()
526 mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200); in mt76x0_phy_tssi_dc_calibrate()
527 dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_dc_calibrate()
530 mt76_wr(dev, MT_RF_BYPASS_0, 0); in mt76x0_phy_tssi_dc_calibrate()
532 mt76_wr(dev, MT_BBP(TXBE, 6), 0); in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
536 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
539 mt76x0_rf_rmw(dev, MT_RF(0, 67), 0xf, 0x4); in mt76x0_phy_tssi_dc_calibrate()
543 mt76x0_phy_tssi_adc_calibrate(struct mt76x02_dev *dev, s16 *ltssi, in mt76x0_phy_tssi_adc_calibrate() argument
546 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x0_phy_tssi_adc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
552 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { in mt76x0_phy_tssi_adc_calibrate()
553 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); in mt76x0_phy_tssi_adc_calibrate()
557 *ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_adc_calibrate()
562 mt76_wr(dev, MT_BBP(CORE, 34), 0x80041); in mt76x0_phy_tssi_adc_calibrate()
563 info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_adc_calibrate()
566 mt76_wr(dev, MT_BBP(CORE, 34), 0x80042); in mt76x0_phy_tssi_adc_calibrate()
567 info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_adc_calibrate()
570 mt76_wr(dev, MT_BBP(CORE, 34), 0x80043); in mt76x0_phy_tssi_adc_calibrate()
571 info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; in mt76x0_phy_tssi_adc_calibrate()
576 static u8 mt76x0_phy_get_rf_pa_mode(struct mt76x02_dev *dev, in mt76x0_phy_get_rf_pa_mode() argument
582 val = mt76_rr(dev, reg); in mt76x0_phy_get_rf_pa_mode()
587 mt76x0_phy_get_target_power(struct mt76x02_dev *dev, u8 tx_mode, in mt76x0_phy_get_target_power() argument
593 cur_power = mt76_rr(dev, MT_TX_ALC_CFG_0) & MT_TX_ALC_CFG_0_CH_INIT_0; in mt76x0_phy_get_target_power()
598 *target_power = cur_power + dev->rate_power.cck[tx_rate]; in mt76x0_phy_get_target_power()
599 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, tx_rate); in mt76x0_phy_get_target_power()
635 *target_power = cur_power + dev->rate_power.ofdm[index]; in mt76x0_phy_get_target_power()
636 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, index + 4); in mt76x0_phy_get_target_power()
647 *target_power += dev->rate_power.vht[tx_rate - 8]; in mt76x0_phy_get_target_power()
649 *target_power += dev->rate_power.ht[tx_rate]; in mt76x0_phy_get_target_power()
651 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate); in mt76x0_phy_get_target_power()
659 *target_power = cur_power + dev->rate_power.ht[tx_rate]; in mt76x0_phy_get_target_power()
660 *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate); in mt76x0_phy_get_target_power()
697 mt76x0_phy_get_delta_power(struct mt76x02_dev *dev, u8 tx_mode, in mt76x0_phy_get_delta_power() argument
701 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x0_phy_get_delta_power()
711 err = mt76x02_eeprom_copy(dev, MT_EE_TSSI_BOUND1, bound, in mt76x0_phy_get_delta_power()
720 val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2); in mt76x0_phy_get_delta_power()
727 val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G); in mt76x0_phy_get_delta_power()
748 data = mt76_rr(dev, MT_BBP(CORE, 1)); in mt76x0_phy_get_delta_power()
749 if (is_mt7630(dev) && mt76_is_mmio(&dev->mt76)) { in mt76x0_phy_get_delta_power()
761 data = mt76_rr(dev, MT_BBP(TXBE, 4)); in mt76x0_phy_get_delta_power()
776 tssi_db = mt76x0_phy_lin2db(ltssi - dev->cal.tssi_dc) * tssi_slope; in mt76x0_phy_get_delta_power()
789 ((ltssi - dev->cal.tssi_dc) < 1 && tssi_target < 0)) { in mt76x0_phy_get_delta_power()
794 if ((dev->cal.tssi_target ^ tssi_target) < 0 && in mt76x0_phy_get_delta_power()
795 dev->cal.tssi_target > -4096 && dev->cal.tssi_target < 4096 && in mt76x0_phy_get_delta_power()
798 tssi_target + dev->cal.tssi_target > 0) || in mt76x0_phy_get_delta_power()
800 tssi_target + dev->cal.tssi_target <= 0)) in mt76x0_phy_get_delta_power()
803 dev->cal.tssi_target = tssi_target; in mt76x0_phy_get_delta_power()
805 dev->cal.tssi_target = tssi_target; in mt76x0_phy_get_delta_power()
815 ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP); in mt76x0_phy_get_delta_power()
824 static void mt76x0_phy_tssi_calibrate(struct mt76x02_dev *dev) in mt76x0_phy_tssi_calibrate() argument
831 if (mt76x0_phy_tssi_adc_calibrate(dev, <ssi, tssi_info) < 0) in mt76x0_phy_tssi_calibrate()
835 if (mt76x0_phy_get_target_power(dev, tx_mode, tssi_info, in mt76x0_phy_tssi_calibrate()
839 val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power, in mt76x0_phy_tssi_calibrate()
841 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val); in mt76x0_phy_tssi_calibrate()
844 void mt76x0_phy_set_txpower(struct mt76x02_dev *dev) in mt76x0_phy_set_txpower() argument
846 struct mt76x02_rate_power *t = &dev->rate_power; in mt76x0_phy_set_txpower()
849 mt76x0_get_tx_power_per_rate(dev, dev->mphy.chandef.chan, t); in mt76x0_phy_set_txpower()
850 mt76x0_get_power_info(dev, dev->mphy.chandef.chan, &info); in mt76x0_phy_set_txpower()
853 mt76x02_limit_rate_power(t, dev->txpower_conf); in mt76x0_phy_set_txpower()
854 dev->mphy.txpower_cur = mt76x02_get_max_rate_power(t); in mt76x0_phy_set_txpower()
857 dev->target_power = info; in mt76x0_phy_set_txpower()
858 mt76x02_phy_set_txpower(dev, info, info); in mt76x0_phy_set_txpower()
861 void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on) in mt76x0_phy_calibrate() argument
863 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x0_phy_calibrate()
867 if (is_mt7630(dev)) in mt76x0_phy_calibrate()
871 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0); in mt76x0_phy_calibrate()
872 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value); in mt76x0_phy_calibrate()
875 if (mt76x0_tssi_enabled(dev)) { in mt76x0_phy_calibrate()
876 mt76_wr(dev, MT_MAC_SYS_CTRL, in mt76x0_phy_calibrate()
878 mt76x0_phy_tssi_dc_calibrate(dev); in mt76x0_phy_calibrate()
879 mt76_wr(dev, MT_MAC_SYS_CTRL, in mt76x0_phy_calibrate()
885 tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0); in mt76x0_phy_calibrate()
886 mt76_wr(dev, MT_TX_ALC_CFG_0, 0); in mt76x0_phy_calibrate()
889 reg_val = mt76_rr(dev, MT_BBP(IBI, 9)); in mt76x0_phy_calibrate()
890 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e); in mt76x0_phy_calibrate()
903 mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val); in mt76x0_phy_calibrate()
904 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz); in mt76x0_phy_calibrate()
907 mt76_wr(dev, MT_BBP(IBI, 9), reg_val); in mt76x0_phy_calibrate()
908 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc); in mt76x0_phy_calibrate()
909 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1); in mt76x0_phy_calibrate()
913 void mt76x0_phy_set_channel(struct mt76x02_dev *dev, in mt76x0_phy_set_channel() argument
938 bool scan = test_bit(MT76_SCANNING, &dev->mphy.state); in mt76x0_phy_set_channel()
971 if (mt76_is_usb(&dev->mt76)) { in mt76x0_phy_set_channel()
972 mt76x0_phy_bbp_set_bw(dev, chandef->width); in mt76x0_phy_set_channel()
979 mt76_wr(dev, MT_TX_SW_CFG0, val); in mt76x0_phy_set_channel()
981 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index); in mt76x0_phy_set_channel()
982 mt76x02_phy_set_band(dev, chandef->chan->band, in mt76x0_phy_set_channel()
985 mt76_rmw(dev, MT_EXT_CCA_CFG, in mt76x0_phy_set_channel()
993 mt76x0_phy_set_band(dev, chandef->chan->band); in mt76x0_phy_set_channel()
994 mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band); in mt76x0_phy_set_channel()
998 mt76_set(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()
1000 mt76_clear(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()
1002 mt76x0_read_rx_gain(dev); in mt76x0_phy_set_channel()
1003 mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band); in mt76x0_phy_set_channel()
1006 mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); in mt76x0_phy_set_channel()
1010 mt76x02_init_agc_gain(dev); in mt76x0_phy_set_channel()
1011 mt76x0_phy_calibrate(dev, false); in mt76x0_phy_set_channel()
1012 mt76x0_phy_set_txpower(dev); in mt76x0_phy_set_channel()
1014 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, in mt76x0_phy_set_channel()
1018 static void mt76x0_phy_temp_sensor(struct mt76x02_dev *dev) in mt76x0_phy_temp_sensor() argument
1023 rf_b7_73 = mt76x0_rf_rr(dev, MT_RF(7, 73)); in mt76x0_phy_temp_sensor()
1024 rf_b0_66 = mt76x0_rf_rr(dev, MT_RF(0, 66)); in mt76x0_phy_temp_sensor()
1025 rf_b0_67 = mt76x0_rf_rr(dev, MT_RF(0, 67)); in mt76x0_phy_temp_sensor()
1027 mt76x0_rf_wr(dev, MT_RF(7, 73), 0x02); in mt76x0_phy_temp_sensor()
1028 mt76x0_rf_wr(dev, MT_RF(0, 66), 0x23); in mt76x0_phy_temp_sensor()
1029 mt76x0_rf_wr(dev, MT_RF(0, 67), 0x01); in mt76x0_phy_temp_sensor()
1031 mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055); in mt76x0_phy_temp_sensor()
1032 if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) { in mt76x0_phy_temp_sensor()
1033 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4)); in mt76x0_phy_temp_sensor()
1037 val = mt76_rr(dev, MT_BBP(CORE, 35)); in mt76x0_phy_temp_sensor()
1038 val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25; in mt76x0_phy_temp_sensor()
1040 if (abs(val - dev->cal.temp_vco) > 20) { in mt76x0_phy_temp_sensor()
1041 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, in mt76x0_phy_temp_sensor()
1042 dev->mphy.chandef.chan->hw_value); in mt76x0_phy_temp_sensor()
1043 dev->cal.temp_vco = val; in mt76x0_phy_temp_sensor()
1045 if (abs(val - dev->cal.temp) > 30) { in mt76x0_phy_temp_sensor()
1046 mt76x0_phy_calibrate(dev, false); in mt76x0_phy_temp_sensor()
1047 dev->cal.temp = val; in mt76x0_phy_temp_sensor()
1051 mt76x0_rf_wr(dev, MT_RF(7, 73), rf_b7_73); in mt76x0_phy_temp_sensor()
1052 mt76x0_rf_wr(dev, MT_RF(0, 66), rf_b0_66); in mt76x0_phy_temp_sensor()
1053 mt76x0_rf_wr(dev, MT_RF(0, 67), rf_b0_67); in mt76x0_phy_temp_sensor()
1056 static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev) in mt76x0_phy_set_gain_val() argument
1058 u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust; in mt76x0_phy_set_gain_val()
1060 mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, gain); in mt76x0_phy_set_gain_val()
1062 if ((dev->mphy.chandef.chan->flags & IEEE80211_CHAN_RADAR) && in mt76x0_phy_set_gain_val()
1063 !is_mt7630(dev)) in mt76x0_phy_set_gain_val()
1064 mt76x02_phy_dfs_adjust_agc(dev); in mt76x0_phy_set_gain_val()
1068 mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev) in mt76x0_phy_update_channel_gain() argument
1074 dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76, false); in mt76x0_phy_update_channel_gain()
1075 if (!dev->cal.avg_rssi_all) in mt76x0_phy_update_channel_gain()
1076 dev->cal.avg_rssi_all = -75; in mt76x0_phy_update_channel_gain()
1078 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) + in mt76x0_phy_update_channel_gain()
1079 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev)); in mt76x0_phy_update_channel_gain()
1081 gain_change = dev->cal.low_gain < 0 || in mt76x0_phy_update_channel_gain()
1082 (dev->cal.low_gain & 2) ^ (low_gain & 2); in mt76x0_phy_update_channel_gain()
1083 dev->cal.low_gain = low_gain; in mt76x0_phy_update_channel_gain()
1086 if (mt76x02_phy_adjust_vga_gain(dev)) in mt76x0_phy_update_channel_gain()
1087 mt76x0_phy_set_gain_val(dev); in mt76x0_phy_update_channel_gain()
1091 dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10; in mt76x0_phy_update_channel_gain()
1094 dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta; in mt76x0_phy_update_channel_gain()
1095 mt76x0_phy_set_gain_val(dev); in mt76x0_phy_update_channel_gain()
1098 mt76_rr(dev, MT_RX_STAT_1); in mt76x0_phy_update_channel_gain()
1103 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, in mt76x0_phy_calibration_work() local
1106 mt76x0_phy_update_channel_gain(dev); in mt76x0_phy_calibration_work()
1107 if (mt76x0_tssi_enabled(dev)) in mt76x0_phy_calibration_work()
1108 mt76x0_phy_tssi_calibrate(dev); in mt76x0_phy_calibration_work()
1110 mt76x0_phy_temp_sensor(dev); in mt76x0_phy_calibration_work()
1112 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, in mt76x0_phy_calibration_work()
1116 static void mt76x0_rf_patch_reg_array(struct mt76x02_dev *dev, in mt76x0_rf_patch_reg_array() argument
1127 if (mt76_is_mmio(&dev->mt76)) { in mt76x0_rf_patch_reg_array()
1128 if (is_mt7630(dev)) in mt76x0_rf_patch_reg_array()
1137 if (is_mt7610e(dev)) in mt76x0_rf_patch_reg_array()
1143 if (is_mt7630(dev)) in mt76x0_rf_patch_reg_array()
1145 else if (is_mt7610e(dev)) in mt76x0_rf_patch_reg_array()
1153 mt76x0_rf_wr(dev, reg, val); in mt76x0_rf_patch_reg_array()
1157 static void mt76x0_phy_rf_init(struct mt76x02_dev *dev) in mt76x0_phy_rf_init() argument
1161 mt76x0_rf_patch_reg_array(dev, mt76x0_rf_central_tab, in mt76x0_phy_rf_init()
1163 mt76x0_rf_patch_reg_array(dev, mt76x0_rf_2g_channel_0_tab, in mt76x0_phy_rf_init()
1165 RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab); in mt76x0_phy_rf_init()
1166 RF_RANDOM_WRITE(dev, mt76x0_rf_vga_channel_0_tab); in mt76x0_phy_rf_init()
1172 mt76x0_rf_wr(dev, item->rf_bank_reg, item->value); in mt76x0_phy_rf_init()
1175 mt76x0_rf_wr(dev, item->rf_bank_reg, item->value); in mt76x0_phy_rf_init()
1180 mt76x0_rf_wr(dev, in mt76x0_phy_rf_init()
1190 mt76x0_rf_wr(dev, MT_RF(0, 22), in mt76x0_phy_rf_init()
1191 min_t(u8, dev->cal.rx.freq_offset, 0xbf)); in mt76x0_phy_rf_init()
1192 mt76x0_rf_rr(dev, MT_RF(0, 22)); in mt76x0_phy_rf_init()
1199 mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); in mt76x0_phy_rf_init()
1200 mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7)); in mt76x0_phy_rf_init()
1201 mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7)); in mt76x0_phy_rf_init()
1204 mt76x0_rf_set(dev, MT_RF(0, 4), 0x80); in mt76x0_phy_rf_init()
1207 void mt76x0_phy_init(struct mt76x02_dev *dev) in mt76x0_phy_init() argument
1209 INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work); in mt76x0_phy_init()
1211 mt76x0_phy_ant_select(dev); in mt76x0_phy_init()
1212 mt76x0_phy_rf_init(dev); in mt76x0_phy_init()
1213 mt76x02_phy_set_rxpath(dev); in mt76x0_phy_init()
1214 mt76x02_phy_set_txdac(dev); in mt76x0_phy_init()