Lines Matching refs:dev
15 mt7622_init_tx_queues_multi(struct mt7615_dev *dev) in mt7622_init_tx_queues_multi() argument
27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], in mt7622_init_tx_queues_multi()
34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, in mt7622_init_tx_queues_multi()
40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU, in mt7622_init_tx_queues_multi()
45 mt7615_init_tx_queues(struct mt7615_dev *dev) in mt7615_init_tx_queues() argument
49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL, in mt7615_init_tx_queues()
54 if (!is_mt7615(&dev->mt76)) in mt7615_init_tx_queues()
55 return mt7622_init_tx_queues_multi(dev); in mt7615_init_tx_queues()
57 ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE, in mt7615_init_tx_queues()
62 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU, in mt7615_init_tx_queues()
68 struct mt7615_dev *dev; in mt7615_poll_tx() local
70 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); in mt7615_poll_tx()
71 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt7615_poll_tx()
73 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt7615_poll_tx()
77 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); in mt7615_poll_tx()
79 mt76_connac_irq_enable(&dev->mt76, in mt7615_poll_tx()
80 mt7615_tx_mcu_int_mask(dev)); in mt7615_poll_tx()
82 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt7615_poll_tx()
89 struct mt7615_dev *dev; in mt7615_poll_rx() local
92 dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev); in mt7615_poll_rx()
94 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { in mt7615_poll_rx()
96 queue_work(dev->mt76.wq, &dev->pm.wake_work); in mt7615_poll_rx()
100 mt76_connac_pm_unref(&dev->mphy, &dev->pm); in mt7615_poll_rx()
105 int mt7615_wait_pdma_busy(struct mt7615_dev *dev) in mt7615_wait_pdma_busy() argument
107 struct mt76_dev *mdev = &dev->mt76; in mt7615_wait_pdma_busy()
111 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY); in mt7615_wait_pdma_busy()
113 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) { in mt7615_wait_pdma_busy()
114 dev_err(mdev->dev, "PDMA engine busy\n"); in mt7615_wait_pdma_busy()
121 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, in mt7615_wait_pdma_busy()
123 dev_err(mdev->dev, "PDMA engine tx busy\n"); in mt7615_wait_pdma_busy()
127 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO, in mt7615_wait_pdma_busy()
129 dev_err(mdev->dev, "PSE engine busy\n"); in mt7615_wait_pdma_busy()
133 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, in mt7615_wait_pdma_busy()
135 dev_err(mdev->dev, "PDMA engine busy\n"); in mt7615_wait_pdma_busy()
142 static void mt7622_dma_sched_init(struct mt7615_dev *dev) in mt7622_dma_sched_init() argument
144 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE); in mt7622_dma_sched_init()
147 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE, in mt7622_dma_sched_init()
153 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i), in mt7622_dma_sched_init()
157 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210); in mt7622_dma_sched_init()
158 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210); in mt7622_dma_sched_init()
159 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5); in mt7622_dma_sched_init()
160 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0); in mt7622_dma_sched_init()
162 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f); in mt7622_dma_sched_init()
163 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987); in mt7622_dma_sched_init()
166 static void mt7663_dma_sched_init(struct mt7615_dev *dev) in mt7663_dma_sched_init() argument
170 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), in mt7663_dma_sched_init()
176 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000); in mt7663_dma_sched_init()
178 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037); in mt7663_dma_sched_init()
182 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), in mt7663_dma_sched_init()
185 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)), in mt7663_dma_sched_init()
188 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)), in mt7663_dma_sched_init()
192 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); in mt7663_dma_sched_init()
193 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); in mt7663_dma_sched_init()
194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005); in mt7663_dma_sched_init()
195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0); in mt7663_dma_sched_init()
197 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f); in mt7663_dma_sched_init()
198 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987); in mt7663_dma_sched_init()
201 void mt7615_dma_start(struct mt7615_dev *dev) in mt7615_dma_start() argument
204 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_start()
209 if (is_mt7622(&dev->mt76)) in mt7615_dma_start()
210 mt7622_dma_sched_init(dev); in mt7615_dma_start()
212 if (is_mt7663(&dev->mt76)) { in mt7615_dma_start()
213 mt7663_dma_sched_init(dev); in mt7615_dma_start()
215 mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK); in mt7615_dma_start()
220 int mt7615_dma_init(struct mt7615_dev *dev) in mt7615_dma_init() argument
226 mt76_dma_attach(&dev->mt76); in mt7615_dma_init()
228 mt76_wr(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
233 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
236 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
239 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
242 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
245 if (is_mt7615(&dev->mt76)) { in mt7615_dma_init()
246 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
249 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1); in mt7615_dma_init()
250 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000); in mt7615_dma_init()
251 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000); in mt7615_dma_init()
252 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026); in mt7615_dma_init()
253 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881); in mt7615_dma_init()
254 mt76_set(dev, 0x7158, BIT(16)); in mt7615_dma_init()
255 mt76_clear(dev, 0x7000, BIT(23)); in mt7615_dma_init()
258 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); in mt7615_dma_init()
260 ret = mt7615_init_tx_queues(dev); in mt7615_dma_init()
265 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, in mt7615_dma_init()
271 if (!is_mt7615(&dev->mt76)) in mt7615_dma_init()
274 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, in mt7615_dma_init()
279 mt76_wr(dev, MT_DELAY_INT_CFG, 0); in mt7615_dma_init()
281 ret = mt76_init_queues(dev, mt7615_poll_rx); in mt7615_dma_init()
285 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, in mt7615_dma_init()
287 napi_enable(&dev->mt76.tx_napi); in mt7615_dma_init()
289 mt76_poll(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_init()
295 mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev); in mt7615_dma_init()
296 if (is_mt7663(&dev->mt76)) in mt7615_dma_init()
301 mt76_connac_irq_enable(&dev->mt76, mask); in mt7615_dma_init()
303 mt7615_dma_start(dev); in mt7615_dma_init()
308 void mt7615_dma_cleanup(struct mt7615_dev *dev) in mt7615_dma_cleanup() argument
310 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt7615_dma_cleanup()
313 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); in mt7615_dma_cleanup()
315 mt76_dma_cleanup(&dev->mt76); in mt7615_dma_cleanup()