64 #define MT_TXTIME_THRESH(n)		(MT_TXTIME_THRESH_BASE + ((n) * 4))  argument
67 #define MT_PAGE_COUNT(n)		(MT_PAGE_COUNT_BASE + ((n) * 4))  argument
79 #define MT_GROUP_THRESH(n)		(MT_GROUP_THRESH_BASE + ((n) * 4))  argument
104 #define MT_PSE_FC_P0_MIN_RESERVE	GENMASK(11, 0)
111 #define MT_PSE_FRP_P2_RQ1		GENMASK(11, 9)
115 #define MT_FC_RSV_COUNT_0_P0		GENMASK(11, 0)
119 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0	GENMASK(11, 0)
137 #define MT_AGC(n)			(MT_AGC_BASE + ((n) * 4))  argument
140 #define MT_AGC1(n)			(MT_AGC1_BASE + ((n) * 4))  argument
146 #define MT_RXTD(n)			(MT_RXTD_BASE + ((n) * 4))  argument
156 #define MT_WF_PHY_CR_TSSI(phy, n)	(MT_WF_PHY_CR_TSSI_BASE +	\  argument
158 					 ((n) * 4))
161 #define MT_PHYCTRL(n)			(MT_PHYCTRL_BASE + ((n) * 4))  argument
216 #define MT_AGG_ASRCR_RANGE(val, n)	(((val) >> ((n) << 3)) & GENMASK(5, 0))  argument
232 #define MT_AGG_RETRY_CONTROL_RTS_LIMIT	GENMASK(11, 7)
291 #define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n)	((n) * 2)  argument
320 #define MT_WF_ARB_BCN_START_BSSn(n)	BIT(0 + (n))  argument
322 #define MT_WF_ARB_BCN_START_T_TTTT	BIT(11)
327 #define MT_WF_ARB_BCN_START_BSS0n(n)	BIT((n) ? 16 + ((n) - 1) : 0)  argument
330 #define MT_WF_ARB_BCN_FLUSH_BSSn(n)	BIT(0 + (n))  argument
331 #define MT_WF_ARB_BCN_FLUSH_BSS0n(n)	BIT((n) ? 16 + ((n) - 1) : 0)  argument
334 #define MT_WF_ARB_CAB_START_BSSn(n)	BIT(0 + (n))  argument
335 #define MT_WF_ARB_CAB_START_BSS0n(n)	BIT((n) ? 16 + ((n) - 1) : 0)  argument
338 #define MT_WF_ARB_CAB_FLUSH_BSSn(n)	BIT(0 + (n))  argument
339 #define MT_WF_ARB_CAB_FLUSH_BSS0n(n)	BIT((n) ? 16 + ((n) - 1) : 0)  argument
341 #define MT_WF_ARB_CAB_COUNT(n)		MT_WF_ARB(0x128 + (n) * 4)  argument
344 #define MT_WF_ARB_CAB_COUNT_B0_REG(n)	MT_WF_ARB_CAB_COUNT(((n) > 12 ? 2 : \  argument
345 							     ((n) > 4 ? 1 : 0)))
346 #define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n)	(((n) > 12 ? (n) - 12 : \  argument
347 					 ((n) > 4 ? (n) - 4 : \
348 					  (n) ? (n) + 3 : 0)) * 4)
359 #define MT_TMAC_TCR_PRE_RTS_GUARD	GENMASK(11, 8)
423 #define MT_WF_RFCR_DROP_OTHER_BEACON	BIT(11)
481 #define MT_WTBL_OFF(n)			(MT_WTBL_OFF_BASE + (n))  argument
485 #define MT_WTBL_UPDATE_WTBL2		BIT(11)
496 #define MT_LPON(n)			(MT_LPON_BASE + (n))  argument
520 #define MT_LPON_SBTOR(n)		MT_LPON(0x0a0)  argument
525 #define MT_INT_WAKEUP(n)		(MT_INT_WAKEUP_BASE + (n))  argument
527 #define MT_HW_INT_STATUS(n)		MT_INT_WAKEUP(0x3c + (n) * 8)  argument
528 #define MT_HW_INT_MASK(n)		MT_INT_WAKEUP(0x40 + (n) * 8)  argument
541 #define MT_WTBL_RIUCR1_RATE0		GENMASK(11, 0)
560 #define MT_MIB_CTL_PSCCA_TIME		GENMASK(13, 11)
573 #define MT_TX_AGG_CNT(n)		MT_MIB(0xa8 + ((n) << 2))  argument
669 #define MT_WTBL1_W2_AMPDU_FACTOR	GENMASK(13, 11)
690 #define MT_WTBL1_W3_WTBL2_ENTRY_ID	GENMASK(15, 11)
699 #define MT_WTBL1_W4_WTBL3_ENTRY_ID	GENMASK(16, 11)
708 #define MT_WTBL2_W2_TID0_SN		GENMASK(11, 0)
739 #define MT_WTBL2_W9_CHANGE_BW_RATE	GENMASK(13, 11)
749 #define MT_WTBL2_W10_RATE1		GENMASK(11, 0)