Lines Matching refs:dev
24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) in mt76_stop_tx_ac() argument
26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); in mt76_stop_tx_ac()
30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) in mt76_start_tx_ac() argument
32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); in mt76_start_tx_ac()
35 void mt7603_mac_reset_counters(struct mt7603_dev *dev) in mt7603_mac_reset_counters() argument
40 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt7603_mac_reset_counters()
42 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); in mt7603_mac_reset_counters()
45 void mt7603_mac_set_timing(struct mt7603_dev *dev) in mt7603_mac_set_timing() argument
51 int offset = 3 * dev->coverage_class; in mt7603_mac_set_timing()
54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; in mt7603_mac_set_timing()
63 mt76_set(dev, MT_ARB_SCR, in mt7603_mac_set_timing()
67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); in mt7603_mac_set_timing()
68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); in mt7603_mac_set_timing()
69 mt76_wr(dev, MT_IFS, in mt7603_mac_set_timing()
73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); in mt7603_mac_set_timing()
75 if (dev->slottime < 20 || is_5ghz) in mt7603_mac_set_timing()
80 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); in mt7603_mac_set_timing()
82 mt76_clear(dev, MT_ARB_SCR, in mt7603_mac_set_timing()
87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) in mt7603_wtbl_update() argument
89 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, in mt7603_wtbl_update()
92 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); in mt7603_wtbl_update()
124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, in mt7603_wtbl_init() argument
145 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); in mt7603_wtbl_init()
147 mt76_set(dev, addr + 0 * 4, w0); in mt7603_wtbl_init()
148 mt76_set(dev, addr + 1 * 4, w1); in mt7603_wtbl_init()
149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); in mt7603_wtbl_init()
151 mt76_stop_tx_ac(dev, GENMASK(3, 0)); in mt7603_wtbl_init()
154 mt76_wr(dev, addr + i, 0); in mt7603_wtbl_init()
155 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); in mt7603_wtbl_init()
156 mt76_start_tx_ac(dev, GENMASK(3, 0)); in mt7603_wtbl_init()
160 mt76_wr(dev, addr + i, 0); in mt7603_wtbl_init()
164 mt76_wr(dev, addr + i, 0); in mt7603_wtbl_init()
166 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); in mt7603_wtbl_init()
170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) in mt7603_wtbl_set_skip_tx() argument
173 u32 val = mt76_rr(dev, addr + 3 * 4); in mt7603_wtbl_set_skip_tx()
178 mt76_wr(dev, addr + 3 * 4, val); in mt7603_wtbl_set_skip_tx()
181 void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort) in mt7603_filter_tx() argument
194 mt7603_wtbl_set_skip_tx(dev, idx, true); in mt7603_filter_tx()
196 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | in mt7603_filter_tx()
205 mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask); in mt7603_filter_tx()
206 mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000); in mt7603_filter_tx()
207 mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask); in mt7603_filter_tx()
209 mt76_wr(dev, MT_TX_ABORT, 0); in mt7603_filter_tx()
212 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | in mt7603_filter_tx()
218 mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000); in mt7603_filter_tx()
221 WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY); in mt7603_filter_tx()
223 mt7603_wtbl_set_skip_tx(dev, idx, false); in mt7603_filter_tx()
226 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, in mt7603_wtbl_set_smps() argument
234 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled); in mt7603_wtbl_set_smps()
238 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, in mt7603_wtbl_set_ps() argument
244 spin_lock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
249 mt76_wr(dev, MT_PSE_RTA, in mt7603_wtbl_set_ps()
256 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); in mt7603_wtbl_set_ps()
259 mt7603_filter_tx(dev, sta->vif->idx, idx, false); in mt7603_wtbl_set_ps()
262 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_set_ps()
263 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE, in mt7603_wtbl_set_ps()
265 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_set_ps()
269 spin_unlock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
272 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) in mt7603_wtbl_clear() argument
291 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); in mt7603_wtbl_clear()
293 mt76_wr(dev, addr + 0 * 4, in mt7603_wtbl_clear()
297 mt76_wr(dev, addr + 1 * 4, 0); in mt7603_wtbl_clear()
298 mt76_wr(dev, addr + 2 * 4, 0); in mt7603_wtbl_clear()
300 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_clear()
302 mt76_wr(dev, addr + 3 * 4, in mt7603_wtbl_clear()
307 mt76_wr(dev, addr + 4 * 4, in mt7603_wtbl_clear()
312 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); in mt7603_wtbl_clear()
317 mt76_wr(dev, addr + (15 * 4), 0); in mt7603_wtbl_clear()
319 mt76_stop_tx_ac(dev, GENMASK(3, 0)); in mt7603_wtbl_clear()
321 mt76_wr(dev, addr + (i * 4), 0); in mt7603_wtbl_clear()
322 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); in mt7603_wtbl_clear()
323 mt76_start_tx_ac(dev, GENMASK(3, 0)); in mt7603_wtbl_clear()
325 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR); in mt7603_wtbl_clear()
326 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR); in mt7603_wtbl_clear()
327 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); in mt7603_wtbl_clear()
330 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta) in mt7603_wtbl_update_cap() argument
344 val = mt76_rr(dev, addr + 2 * 4); in mt7603_wtbl_update_cap()
357 mt76_wr(dev, addr + 2 * 4, val); in mt7603_wtbl_update_cap()
360 val = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_update_cap()
367 mt76_wr(dev, addr + 9 * 4, val); in mt7603_wtbl_update_cap()
370 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid) in mt7603_mac_rx_ba_reset() argument
372 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr)); in mt7603_mac_rx_ba_reset()
373 mt76_wr(dev, MT_BA_CONTROL_1, in mt7603_mac_rx_ba_reset()
379 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, in mt7603_mac_tx_ba_reset() argument
391 mt76_clear(dev, addr + (15 * 4), tid_mask); in mt7603_mac_tx_ba_reset()
403 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val); in mt7603_mac_tx_ba_reset()
406 void mt7603_mac_sta_poll(struct mt7603_dev *dev) in mt7603_mac_sta_poll() argument
426 spin_lock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
427 if (list_empty(&dev->mt76.sta_poll_list)) { in mt7603_mac_sta_poll()
428 spin_unlock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
432 msta = list_first_entry(&dev->mt76.sta_poll_list, in mt7603_mac_sta_poll()
435 spin_unlock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
441 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); in mt7603_mac_sta_poll()
451 mt7603_wtbl_update(dev, msta->wcid.idx, in mt7603_mac_sta_poll()
462 struct mt76_queue *q = dev->mphy.q_tx[i]; in mt7603_mac_sta_poll()
479 spin_lock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
480 dev->mphy.chan_state->cc_tx += total_airtime; in mt7603_mac_sta_poll()
481 spin_unlock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
485 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) in mt7603_rx_get_wcid() argument
493 wcid = rcu_dereference(dev->mt76.wcid[idx]); in mt7603_rx_get_wcid()
508 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb) in mt7603_mac_fill_rx() argument
526 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; in mt7603_mac_fill_rx()
530 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); in mt7603_mac_fill_rx()
607 if (dev->rx_ampdu_ts != status->timestamp) { in mt7603_mac_fill_rx()
608 if (!++dev->ampdu_ref) in mt7603_mac_fill_rx()
609 dev->ampdu_ref++; in mt7603_mac_fill_rx()
611 dev->rx_ampdu_ts = status->timestamp; in mt7603_mac_fill_rx()
613 status->ampdu_ref = dev->ampdu_ref; in mt7603_mac_fill_rx()
631 i = mt76_get_rate(&dev->mt76, sband, i, cck); in mt7603_mac_fill_rx()
653 status->chains = dev->mphy.antenna_mask; in mt7603_mac_fill_rx()
655 dev->rssi_offset[0]; in mt7603_mac_fill_rx()
657 dev->rssi_offset[1]; in mt7603_mac_fill_rx()
690 mt7603_mac_tx_rate_val(struct mt7603_dev *dev, in mt7603_mac_tx_rate_val() argument
707 int band = dev->mphy.chandef.chan->band; in mt7603_mac_tx_rate_val()
711 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; in mt7603_mac_tx_rate_val()
730 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, in mt7603_wtbl_set_rates() argument
742 u32 w9 = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_set_rates()
746 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) in mt7603_wtbl_set_rates()
792 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); in mt7603_wtbl_set_rates()
796 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw); in mt7603_wtbl_set_rates()
808 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); in mt7603_wtbl_set_rates()
814 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); in mt7603_wtbl_set_rates()
820 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); in mt7603_wtbl_set_rates()
827 mt76_wr(dev, MT_WTBL_RIUCR0, w9); in mt7603_wtbl_set_rates()
829 mt76_wr(dev, MT_WTBL_RIUCR1, in mt7603_wtbl_set_rates()
834 mt76_wr(dev, MT_WTBL_RIUCR2, in mt7603_wtbl_set_rates()
840 mt76_wr(dev, MT_WTBL_RIUCR3, in mt7603_wtbl_set_rates()
845 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ in mt7603_wtbl_set_rates()
846 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; in mt7603_wtbl_set_rates()
848 mt76_wr(dev, MT_WTBL_UPDATE, in mt7603_wtbl_set_rates()
854 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); in mt7603_wtbl_set_rates()
889 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, in mt7603_wtbl_set_key() argument
906 mt76_wr_copy(dev, addr, key_data, key_len); in mt7603_wtbl_set_key()
909 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher); in mt7603_wtbl_set_key()
911 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); in mt7603_wtbl_set_key()
912 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key); in mt7603_wtbl_set_key()
918 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi, in mt7603_mac_write_txwi() argument
928 struct mt76_queue *q = dev->mphy.q_tx[qid]; in mt7603_mac_write_txwi()
998 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw); in mt7603_mac_write_txwi()
1052 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); in mt7603_tx_prepare_skb() local
1059 wcid = &dev->global_sta.wcid; in mt7603_tx_prepare_skb()
1067 mt7603_wtbl_set_ps(dev, msta, false); in mt7603_tx_prepare_skb()
1075 spin_lock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1076 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], in mt7603_tx_prepare_skb()
1079 spin_unlock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1082 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, in mt7603_tx_prepare_skb()
1089 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta, in mt7603_fill_txs() argument
1154 spin_lock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1156 mt7603_wtbl_set_rates(dev, sta, NULL, in mt7603_fill_txs()
1160 spin_unlock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1197 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) in mt7603_fill_txs()
1198 sband = &dev->mphy.sband_5g.sband; in mt7603_fill_txs()
1200 sband = &dev->mphy.sband_2g.sband; in mt7603_fill_txs()
1202 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, in mt7603_fill_txs()
1224 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid, in mt7603_mac_add_txs_skb() argument
1227 struct mt76_dev *mdev = &dev->mt76; in mt7603_mac_add_txs_skb()
1241 if (!mt7603_fill_txs(dev, sta, info, txs_data)) { in mt7603_mac_add_txs_skb()
1253 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data) in mt7603_mac_add_txs() argument
1274 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); in mt7603_mac_add_txs()
1282 spin_lock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_add_txs()
1283 list_add_tail(&msta->wcid.poll_list, &dev->mt76.sta_poll_list); in mt7603_mac_add_txs()
1284 spin_unlock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_add_txs()
1287 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data)) in mt7603_mac_add_txs()
1293 if (mt7603_fill_txs(dev, msta, &info, txs_data)) { in mt7603_mac_add_txs()
1294 spin_lock_bh(&dev->mt76.rx_lock); in mt7603_mac_add_txs()
1295 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info); in mt7603_mac_add_txs()
1296 spin_unlock_bh(&dev->mt76.rx_lock); in mt7603_mac_add_txs()
1305 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); in mt7603_tx_complete_skb() local
1313 dev->tx_hang_check = 0; in mt7603_tx_complete_skb()
1318 wait_for_wpdma(struct mt7603_dev *dev) in wait_for_wpdma() argument
1320 return mt76_poll(dev, MT_WPDMA_GLO_CFG, in wait_for_wpdma()
1326 static void mt7603_pse_reset(struct mt7603_dev *dev) in mt7603_pse_reset() argument
1329 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) in mt7603_pse_reset()
1330 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); in mt7603_pse_reset()
1333 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); in mt7603_pse_reset()
1335 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, in mt7603_pse_reset()
1338 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; in mt7603_pse_reset()
1339 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); in mt7603_pse_reset()
1341 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1342 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); in mt7603_pse_reset()
1345 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) in mt7603_pse_reset()
1346 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1349 void mt7603_mac_dma_start(struct mt7603_dev *dev) in mt7603_mac_dma_start() argument
1351 mt7603_mac_start(dev); in mt7603_mac_dma_start()
1353 wait_for_wpdma(dev); in mt7603_mac_dma_start()
1356 mt76_set(dev, MT_WPDMA_GLO_CFG, in mt7603_mac_dma_start()
1362 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL); in mt7603_mac_dma_start()
1365 void mt7603_mac_start(struct mt7603_dev *dev) in mt7603_mac_start() argument
1367 mt76_clear(dev, MT_ARB_SCR, in mt7603_mac_start()
1369 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); in mt7603_mac_start()
1370 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); in mt7603_mac_start()
1373 void mt7603_mac_stop(struct mt7603_dev *dev) in mt7603_mac_stop() argument
1375 mt76_set(dev, MT_ARB_SCR, in mt7603_mac_stop()
1377 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); in mt7603_mac_stop()
1378 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); in mt7603_mac_stop()
1381 void mt7603_pse_client_reset(struct mt7603_dev *dev) in mt7603_pse_client_reset() argument
1385 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + in mt7603_pse_client_reset()
1389 mt76_clear(dev, addr, in mt7603_pse_client_reset()
1396 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF); in mt7603_pse_client_reset()
1397 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); in mt7603_pse_client_reset()
1398 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S, in mt7603_pse_client_reset()
1401 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); in mt7603_pse_client_reset()
1402 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); in mt7603_pse_client_reset()
1405 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S, in mt7603_pse_client_reset()
1409 mt76_clear(dev, addr, in mt7603_pse_client_reset()
1414 static void mt7603_dma_sched_reset(struct mt7603_dev *dev) in mt7603_dma_sched_reset() argument
1416 if (!is_mt7628(dev)) in mt7603_dma_sched_reset()
1419 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); in mt7603_dma_sched_reset()
1420 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); in mt7603_dma_sched_reset()
1423 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) in mt7603_mac_watchdog_reset() argument
1425 int beacon_int = dev->mt76.beacon_int; in mt7603_mac_watchdog_reset()
1426 u32 mask = dev->mt76.mmio.irqmask; in mt7603_mac_watchdog_reset()
1429 ieee80211_stop_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1430 set_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1433 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1435 mt76_worker_disable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1436 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1437 napi_disable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1438 napi_disable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1439 napi_disable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1441 mutex_lock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1443 mt7603_beacon_set_timer(dev, -1, 0); in mt7603_mac_watchdog_reset()
1445 mt7603_mac_stop(dev); in mt7603_mac_watchdog_reset()
1447 mt76_clear(dev, MT_WPDMA_GLO_CFG, in mt7603_mac_watchdog_reset()
1452 mt7603_irq_disable(dev, mask); in mt7603_mac_watchdog_reset()
1454 mt7603_pse_client_reset(dev); in mt7603_mac_watchdog_reset()
1456 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); in mt7603_mac_watchdog_reset()
1458 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt7603_mac_watchdog_reset()
1460 mt7603_dma_sched_reset(dev); in mt7603_mac_watchdog_reset()
1462 mt76_tx_status_check(&dev->mt76, true); in mt7603_mac_watchdog_reset()
1464 mt76_for_each_q_rx(&dev->mt76, i) { in mt7603_mac_watchdog_reset()
1465 mt76_queue_rx_reset(dev, i); in mt7603_mac_watchdog_reset()
1468 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || in mt7603_mac_watchdog_reset()
1469 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY) in mt7603_mac_watchdog_reset()
1470 mt7603_pse_reset(dev); in mt7603_mac_watchdog_reset()
1472 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { in mt7603_mac_watchdog_reset()
1473 mt7603_mac_dma_start(dev); in mt7603_mac_watchdog_reset()
1475 mt7603_irq_enable(dev, mask); in mt7603_mac_watchdog_reset()
1477 clear_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1480 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1482 mt76_worker_enable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1484 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1485 mt7603_beacon_set_timer(dev, -1, beacon_int); in mt7603_mac_watchdog_reset()
1488 napi_enable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1489 napi_schedule(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1491 napi_enable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1492 napi_schedule(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1494 napi_enable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1495 napi_schedule(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1498 ieee80211_wake_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1499 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1502 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index) in mt7603_dma_debug() argument
1506 mt76_wr(dev, MT_WPDMA_DEBUG, in mt7603_dma_debug()
1510 val = mt76_rr(dev, MT_WPDMA_DEBUG); in mt7603_dma_debug()
1514 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev) in mt7603_rx_fifo_busy() argument
1516 if (is_mt7628(dev)) in mt7603_rx_fifo_busy()
1517 return mt7603_dma_debug(dev, 9) & BIT(9); in mt7603_rx_fifo_busy()
1519 return mt7603_dma_debug(dev, 2) & BIT(8); in mt7603_rx_fifo_busy()
1522 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev) in mt7603_rx_dma_busy() argument
1524 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) in mt7603_rx_dma_busy()
1527 return mt7603_rx_fifo_busy(dev); in mt7603_rx_dma_busy()
1530 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev) in mt7603_tx_dma_busy() argument
1534 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY)) in mt7603_tx_dma_busy()
1537 val = mt7603_dma_debug(dev, 9); in mt7603_tx_dma_busy()
1541 static bool mt7603_tx_hang(struct mt7603_dev *dev) in mt7603_tx_hang() argument
1548 q = dev->mphy.q_tx[i]; in mt7603_tx_hang()
1553 prev_dma_idx = dev->tx_dma_idx[i]; in mt7603_tx_hang()
1555 dev->tx_dma_idx[i] = dma_idx; in mt7603_tx_hang()
1565 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) in mt7603_rx_pse_busy() argument
1569 if (mt7603_rx_fifo_busy(dev)) in mt7603_rx_pse_busy()
1572 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); in mt7603_rx_pse_busy()
1573 mt76_wr(dev, addr, 3); in mt7603_rx_pse_busy()
1574 val = mt76_rr(dev, addr) >> 16; in mt7603_rx_pse_busy()
1579 if (is_mt7628(dev)) in mt7603_rx_pse_busy()
1587 if (mt76_rr(dev, MT_INT_SOURCE_CSR) & in mt7603_rx_pse_busy()
1595 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter, in mt7603_watchdog_check() argument
1597 bool (*check)(struct mt7603_dev *dev)) in mt7603_watchdog_check() argument
1599 if (dev->reset_test == cause + 1) { in mt7603_watchdog_check()
1600 dev->reset_test = 0; in mt7603_watchdog_check()
1605 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) { in mt7603_watchdog_check()
1616 dev->cur_reset_cause = cause; in mt7603_watchdog_check()
1617 dev->reset_cause[cause]++; in mt7603_watchdog_check()
1623 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76); in mt7603_update_channel() local
1627 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); in mt7603_update_channel()
1631 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) in mt7603_edcca_set_strict() argument
1635 if (val == dev->ed_strict_mode) in mt7603_edcca_set_strict()
1638 dev->ed_strict_mode = val; in mt7603_edcca_set_strict()
1641 if (!dev->ed_monitor) in mt7603_edcca_set_strict()
1646 if (dev->ed_monitor && !dev->ed_strict_mode) in mt7603_edcca_set_strict()
1651 mt76_wr(dev, MT_RXTD(6), rxtd_6); in mt7603_edcca_set_strict()
1653 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN, in mt7603_edcca_set_strict()
1654 dev->ed_monitor && !dev->ed_strict_mode); in mt7603_edcca_set_strict()
1658 mt7603_edcca_check(struct mt7603_dev *dev) in mt7603_edcca_check() argument
1660 u32 val = mt76_rr(dev, MT_AGC(41)); in mt7603_edcca_check()
1666 if (!dev->ed_monitor) in mt7603_edcca_check()
1673 if (dev->mphy.antenna_mask & BIT(1)) { in mt7603_edcca_check()
1682 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1683 dev->ed_strong_signal++; in mt7603_edcca_check()
1684 else if (dev->ed_strong_signal > 0) in mt7603_edcca_check()
1685 dev->ed_strong_signal--; in mt7603_edcca_check()
1688 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK; in mt7603_edcca_check()
1690 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); in mt7603_edcca_check()
1691 dev->ed_time = cur_time; in mt7603_edcca_check()
1697 if (dev->ed_trigger < 0) in mt7603_edcca_check()
1698 dev->ed_trigger = 0; in mt7603_edcca_check()
1699 dev->ed_trigger++; in mt7603_edcca_check()
1701 if (dev->ed_trigger > 0) in mt7603_edcca_check()
1702 dev->ed_trigger = 0; in mt7603_edcca_check()
1703 dev->ed_trigger--; in mt7603_edcca_check()
1706 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || in mt7603_edcca_check()
1707 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { in mt7603_edcca_check()
1708 mt7603_edcca_set_strict(dev, true); in mt7603_edcca_check()
1709 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { in mt7603_edcca_check()
1710 mt7603_edcca_set_strict(dev, false); in mt7603_edcca_check()
1713 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1714 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1715 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1716 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1719 void mt7603_cca_stats_reset(struct mt7603_dev *dev) in mt7603_cca_stats_reset() argument
1721 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); in mt7603_cca_stats_reset()
1722 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); in mt7603_cca_stats_reset()
1723 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN); in mt7603_cca_stats_reset()
1727 mt7603_adjust_sensitivity(struct mt7603_dev *dev) in mt7603_adjust_sensitivity() argument
1729 u32 agc0 = dev->agc0, agc3 = dev->agc3; in mt7603_adjust_sensitivity()
1732 if (!dev->sensitivity || dev->sensitivity < -100) { in mt7603_adjust_sensitivity()
1733 dev->sensitivity = 0; in mt7603_adjust_sensitivity()
1734 } else if (dev->sensitivity <= -84) { in mt7603_adjust_sensitivity()
1735 adj = 7 + (dev->sensitivity + 92) / 2; in mt7603_adjust_sensitivity()
1741 } else if (dev->sensitivity <= -72) { in mt7603_adjust_sensitivity()
1742 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1751 if (dev->sensitivity > -54) in mt7603_adjust_sensitivity()
1752 dev->sensitivity = -54; in mt7603_adjust_sensitivity()
1754 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1765 mt76_wr(dev, MT_AGC(0), agc0); in mt7603_adjust_sensitivity()
1766 mt76_wr(dev, MT_AGC1(0), agc0); in mt7603_adjust_sensitivity()
1768 mt76_wr(dev, MT_AGC(3), agc3); in mt7603_adjust_sensitivity()
1769 mt76_wr(dev, MT_AGC1(3), agc3); in mt7603_adjust_sensitivity()
1773 mt7603_false_cca_check(struct mt7603_dev *dev) in mt7603_false_cca_check() argument
1780 if (!dev->dynamic_sensitivity) in mt7603_false_cca_check()
1783 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); in mt7603_false_cca_check()
1787 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); in mt7603_false_cca_check()
1791 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; in mt7603_false_cca_check()
1792 dev->false_cca_cck = pd_cck - mdrdy_cck; in mt7603_false_cca_check()
1794 mt7603_cca_stats_reset(dev); in mt7603_false_cca_check()
1796 min_signal = mt76_get_min_avg_rssi(&dev->mt76, false); in mt7603_false_cca_check()
1798 dev->sensitivity = 0; in mt7603_false_cca_check()
1799 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1805 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; in mt7603_false_cca_check()
1807 dev->sensitivity < -100 + dev->sensitivity_limit) { in mt7603_false_cca_check()
1808 if (!dev->sensitivity) in mt7603_false_cca_check()
1809 dev->sensitivity = -92; in mt7603_false_cca_check()
1811 dev->sensitivity += 2; in mt7603_false_cca_check()
1812 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1814 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { in mt7603_false_cca_check()
1815 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1816 if (!dev->sensitivity) in mt7603_false_cca_check()
1819 dev->sensitivity -= 2; in mt7603_false_cca_check()
1822 if (dev->sensitivity && dev->sensitivity > min_signal) { in mt7603_false_cca_check()
1823 dev->sensitivity = min_signal; in mt7603_false_cca_check()
1824 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1828 mt7603_adjust_sensitivity(dev); in mt7603_false_cca_check()
1833 struct mt7603_dev *dev = container_of(work, struct mt7603_dev, in mt7603_mac_work() local
1838 mt76_tx_status_check(&dev->mt76, false); in mt7603_mac_work()
1840 mutex_lock(&dev->mt76.mutex); in mt7603_mac_work()
1842 dev->mphy.mac_work_count++; in mt7603_mac_work()
1843 mt76_update_survey(&dev->mphy); in mt7603_mac_work()
1844 mt7603_edcca_check(dev); in mt7603_mac_work()
1847 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt7603_mac_work()
1849 dev->mphy.aggr_stats[idx++] += val & 0xffff; in mt7603_mac_work()
1850 dev->mphy.aggr_stats[idx++] += val >> 16; in mt7603_mac_work()
1853 if (dev->mphy.mac_work_count == 10) in mt7603_mac_work()
1854 mt7603_false_cca_check(dev); in mt7603_mac_work()
1856 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, in mt7603_mac_work()
1859 mt7603_watchdog_check(dev, &dev->beacon_check, in mt7603_mac_work()
1862 mt7603_watchdog_check(dev, &dev->tx_hang_check, in mt7603_mac_work()
1865 mt7603_watchdog_check(dev, &dev->tx_dma_check, in mt7603_mac_work()
1868 mt7603_watchdog_check(dev, &dev->rx_dma_check, in mt7603_mac_work()
1871 mt7603_watchdog_check(dev, &dev->mcu_hang, in mt7603_mac_work()
1874 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { in mt7603_mac_work()
1875 dev->beacon_check = 0; in mt7603_mac_work()
1876 dev->tx_dma_check = 0; in mt7603_mac_work()
1877 dev->tx_hang_check = 0; in mt7603_mac_work()
1878 dev->rx_dma_check = 0; in mt7603_mac_work()
1879 dev->rx_pse_check = 0; in mt7603_mac_work()
1880 dev->mcu_hang = 0; in mt7603_mac_work()
1881 dev->rx_dma_idx = ~0; in mt7603_mac_work()
1882 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); in mt7603_mac_work()
1884 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1887 if (dev->mphy.mac_work_count >= 10) in mt7603_mac_work()
1888 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1890 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_work()
1893 mt7603_mac_watchdog_reset(dev); in mt7603_mac_work()
1895 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, in mt7603_mac_work()