Lines Matching refs:trans
36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) in iwl_trans_pcie_dump_regs() argument
42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_regs()
66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); in iwl_trans_pcie_dump_regs()
70 IWL_ERR(trans, "iwlwifi device config registers:\n"); in iwl_trans_pcie_dump_regs()
76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); in iwl_trans_pcie_dump_regs()
78 *ptr = iwl_read32(trans, i); in iwl_trans_pcie_dump_regs()
83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); in iwl_trans_pcie_dump_regs()
98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", in iwl_trans_pcie_dump_regs()
111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", in iwl_trans_pcie_dump_regs()
124 IWL_ERR(trans, "Read failed at 0x%X\n", i); in iwl_trans_pcie_dump_regs()
130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, in iwl_trans_pcie_sw_reset() argument
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_trans_pcie_sw_reset()
135 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_sw_reset()
139 iwl_set_bit(trans, CSR_RESET, in iwl_trans_pcie_sw_reset()
145 return iwl_pcie_prepare_card_hw(trans); in iwl_trans_pcie_sw_reset()
150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) in iwl_pcie_free_fw_monitor() argument
152 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
157 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, in iwl_pcie_alloc_fw_monitor_block() argument
168 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
182 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
187 IWL_INFO(trans, in iwl_pcie_alloc_fw_monitor_block()
197 IWL_ERR(trans, in iwl_pcie_alloc_fw_monitor_block()
207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) in iwl_pcie_alloc_fw_monitor() argument
221 iwl_pcie_alloc_fw_monitor_block(trans, max_power); in iwl_pcie_alloc_fw_monitor()
224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_shr() argument
226 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_read_shr()
228 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); in iwl_trans_pcie_read_shr()
231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) in iwl_trans_pcie_write_shr() argument
233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); in iwl_trans_pcie_write_shr()
234 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, in iwl_trans_pcie_write_shr()
238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) in iwl_pcie_set_pwr() argument
240 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
243 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
244 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
248 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, in iwl_pcie_set_pwr()
256 void iwl_pcie_apm_config(struct iwl_trans *trans) in iwl_pcie_apm_config() argument
258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_apm_config()
267 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); in iwl_pcie_apm_config()
270 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
273 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
274 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
276 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
284 static int iwl_pcie_apm_init(struct iwl_trans *trans) in iwl_pcie_apm_init() argument
288 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); in iwl_pcie_apm_init()
296 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
297 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
304 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, in iwl_pcie_apm_init()
308 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); in iwl_pcie_apm_init()
314 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_init()
317 iwl_pcie_apm_config(trans); in iwl_pcie_apm_init()
320 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
321 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); in iwl_pcie_apm_init()
323 ret = iwl_finish_nic_init(trans); in iwl_pcie_apm_init()
327 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
342 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
343 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
344 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); in iwl_pcie_apm_init()
345 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
346 iwl_read_prph(trans, OSC_CLK); in iwl_pcie_apm_init()
356 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
357 iwl_write_prph(trans, APMG_CLK_EN_REG, in iwl_pcie_apm_init()
362 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_init()
366 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, in iwl_pcie_apm_init()
370 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) in iwl_pcie_apm_lp_xtal_enable() argument
390 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
393 ret = iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_apm_lp_xtal_enable()
396 ret = iwl_finish_nic_init(trans); in iwl_pcie_apm_lp_xtal_enable()
400 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
409 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_lp_xtal_enable()
416 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, in iwl_pcie_apm_lp_xtal_enable()
418 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
422 ret = iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_apm_lp_xtal_enable()
424 IWL_ERR(trans, in iwl_pcie_apm_lp_xtal_enable()
428 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); in iwl_pcie_apm_lp_xtal_enable()
429 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | in iwl_pcie_apm_lp_xtal_enable()
434 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); in iwl_pcie_apm_lp_xtal_enable()
435 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & in iwl_pcie_apm_lp_xtal_enable()
442 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_lp_xtal_enable()
449 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_lp_xtal_enable()
452 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
456 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_lp_xtal_enable()
461 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, in iwl_pcie_apm_lp_xtal_enable()
466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) in iwl_pcie_apm_stop_master() argument
472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
473 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop_master()
476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, in iwl_pcie_apm_stop_master()
482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); in iwl_pcie_apm_stop_master()
484 ret = iwl_poll_bit(trans, CSR_RESET, in iwl_pcie_apm_stop_master()
490 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); in iwl_pcie_apm_stop_master()
492 IWL_DEBUG_INFO(trans, "stop master\n"); in iwl_pcie_apm_stop_master()
495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) in iwl_pcie_apm_stop() argument
497 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); in iwl_pcie_apm_stop()
500 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
501 iwl_pcie_apm_init(trans); in iwl_pcie_apm_stop()
504 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
505 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, in iwl_pcie_apm_stop()
507 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
509 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
511 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apm_stop()
515 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_apm_stop()
521 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
524 iwl_pcie_apm_stop_master(trans); in iwl_pcie_apm_stop()
526 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
527 iwl_pcie_apm_lp_xtal_enable(trans); in iwl_pcie_apm_stop()
531 iwl_trans_pcie_sw_reset(trans, false); in iwl_pcie_apm_stop()
537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_apm_stop()
540 static int iwl_pcie_nic_init(struct iwl_trans *trans) in iwl_pcie_nic_init() argument
542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_nic_init()
547 ret = iwl_pcie_apm_init(trans); in iwl_pcie_nic_init()
553 iwl_pcie_set_pwr(trans, false); in iwl_pcie_nic_init()
555 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
558 ret = iwl_pcie_rx_init(trans); in iwl_pcie_nic_init()
563 if (iwl_pcie_tx_init(trans)) { in iwl_pcie_nic_init()
564 iwl_pcie_rx_free(trans); in iwl_pcie_nic_init()
568 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
570 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); in iwl_pcie_nic_init()
571 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); in iwl_pcie_nic_init()
580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) in iwl_pcie_set_hw_ready() argument
584 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
588 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_set_hw_ready()
594 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); in iwl_pcie_set_hw_ready()
596 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); in iwl_pcie_set_hw_ready()
601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) in iwl_pcie_prepare_card_hw() argument
606 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); in iwl_pcie_prepare_card_hw()
608 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
611 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
615 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, in iwl_pcie_prepare_card_hw()
623 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_prepare_card_hw()
627 ret = iwl_pcie_set_hw_ready(trans); in iwl_pcie_prepare_card_hw()
629 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
634 IWL_DEBUG_INFO(trans, in iwl_pcie_prepare_card_hw()
636 trans->csme_own = true; in iwl_pcie_prepare_card_hw()
637 if (trans->trans_cfg->device_family != in iwl_pcie_prepare_card_hw()
639 IWL_ERR(trans, in iwl_pcie_prepare_card_hw()
651 IWL_ERR(trans, "Couldn't prepare the card\n"); in iwl_pcie_prepare_card_hw()
659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk_fh() argument
663 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
666 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
669 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
672 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
676 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
681 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), in iwl_pcie_load_firmware_chunk_fh()
687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, in iwl_pcie_load_firmware_chunk() argument
691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_load_firmware_chunk()
696 if (!iwl_trans_grab_nic_access(trans)) in iwl_pcie_load_firmware_chunk()
699 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, in iwl_pcie_load_firmware_chunk()
701 iwl_trans_release_nic_access(trans); in iwl_pcie_load_firmware_chunk()
706 IWL_ERR(trans, "Failed to load firmware chunk!\n"); in iwl_pcie_load_firmware_chunk()
707 iwl_trans_pcie_dump_regs(trans); in iwl_pcie_load_firmware_chunk()
714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, in iwl_pcie_load_section() argument
722 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", in iwl_pcie_load_section()
725 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
728 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); in iwl_pcie_load_section()
730 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
748 iwl_set_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
752 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, in iwl_pcie_load_section()
756 iwl_clear_bits_prph(trans, LMPM_CHICK, in iwl_pcie_load_section()
760 IWL_ERR(trans, in iwl_pcie_load_section()
767 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections_8000() argument
800 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections_8000()
806 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
811 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); in iwl_pcie_load_cpu_sections_8000()
813 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); in iwl_pcie_load_cpu_sections_8000()
820 iwl_enable_interrupts(trans); in iwl_pcie_load_cpu_sections_8000()
822 if (trans->trans_cfg->gen2) { in iwl_pcie_load_cpu_sections_8000()
824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
827 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
834 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, in iwl_pcie_load_cpu_sections_8000()
841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, in iwl_pcie_load_cpu_sections() argument
866 IWL_DEBUG_FW(trans, in iwl_pcie_load_cpu_sections()
872 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) in iwl_pcie_apply_destination_ini() argument
886 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
889 if (!iwl_trans_dbg_ini_valid(trans)) in iwl_pcie_apply_destination_ini()
894 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); in iwl_pcie_apply_destination_ini()
896 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_pcie_apply_destination_ini()
904 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
907 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
909 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", in iwl_pcie_apply_destination_ini()
912 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, in iwl_pcie_apply_destination_ini()
914 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, in iwl_pcie_apply_destination_ini()
919 void iwl_pcie_apply_destination(struct iwl_trans *trans) in iwl_pcie_apply_destination() argument
921 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
922 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
925 if (iwl_trans_dbg_ini_valid(trans)) { in iwl_pcie_apply_destination()
926 iwl_pcie_apply_destination_ini(trans); in iwl_pcie_apply_destination()
930 IWL_INFO(trans, "Applying debug destination %s\n", in iwl_pcie_apply_destination()
934 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
936 IWL_WARN(trans, "PCI should have external buffer debug\n"); in iwl_pcie_apply_destination()
938 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
944 iwl_write32(trans, addr, val); in iwl_pcie_apply_destination()
947 iwl_set_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
950 iwl_clear_bit(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
953 iwl_write_prph(trans, addr, val); in iwl_pcie_apply_destination()
956 iwl_set_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
959 iwl_clear_bits_prph(trans, addr, BIT(val)); in iwl_pcie_apply_destination()
962 if (iwl_read_prph(trans, addr) & BIT(val)) { in iwl_pcie_apply_destination()
963 IWL_ERR(trans, in iwl_pcie_apply_destination()
970 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
978 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
981 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
985 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, in iwl_pcie_load_given_ucode() argument
997 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode()
1001 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); in iwl_pcie_load_given_ucode()
1007 iwl_write_prph(trans, in iwl_pcie_load_given_ucode()
1012 ret = iwl_pcie_load_cpu_sections(trans, image, 2, in iwl_pcie_load_given_ucode()
1018 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode()
1019 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode()
1021 iwl_enable_interrupts(trans); in iwl_pcie_load_given_ucode()
1024 iwl_write32(trans, CSR_RESET, 0); in iwl_pcie_load_given_ucode()
1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, in iwl_pcie_load_given_ucode_8000() argument
1035 IWL_DEBUG_FW(trans, "working with %s CPU\n", in iwl_pcie_load_given_ucode_8000()
1038 if (iwl_pcie_dbg_on(trans)) in iwl_pcie_load_given_ucode_8000()
1039 iwl_pcie_apply_destination(trans); in iwl_pcie_load_given_ucode_8000()
1041 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", in iwl_pcie_load_given_ucode_8000()
1042 iwl_read_prph(trans, WFPM_GP2)); in iwl_pcie_load_given_ucode_8000()
1049 iwl_write_prph(trans, WFPM_GP2, 0x01010101); in iwl_pcie_load_given_ucode_8000()
1053 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); in iwl_pcie_load_given_ucode_8000()
1056 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, in iwl_pcie_load_given_ucode_8000()
1062 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, in iwl_pcie_load_given_ucode_8000()
1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) in iwl_pcie_check_hw_rf_kill() argument
1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_check_hw_rf_kill()
1069 bool hw_rfkill = iwl_is_rfkill_set(trans); in iwl_pcie_check_hw_rf_kill()
1070 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1074 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1075 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1077 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1079 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1082 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1085 iwl_trans_pcie_rf_kill(trans, report, false); in iwl_pcie_check_hw_rf_kill()
1131 static void iwl_pcie_map_list(struct iwl_trans *trans, in iwl_pcie_map_list() argument
1138 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); in iwl_pcie_map_list()
1139 iwl_clear_bit(trans, causes[i].mask_reg, in iwl_pcie_map_list()
1144 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_non_rx_causes() argument
1146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_non_rx_causes()
1153 iwl_pcie_map_list(trans, causes_list_common, in iwl_pcie_map_non_rx_causes()
1155 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_map_non_rx_causes()
1156 iwl_pcie_map_list(trans, causes_list_bz, in iwl_pcie_map_non_rx_causes()
1159 iwl_pcie_map_list(trans, causes_list_pre_bz, in iwl_pcie_map_non_rx_causes()
1163 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) in iwl_pcie_map_rx_causes() argument
1165 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_map_rx_causes()
1177 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1178 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), in iwl_pcie_map_rx_causes()
1182 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); in iwl_pcie_map_rx_causes()
1187 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); in iwl_pcie_map_rx_causes()
1190 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); in iwl_pcie_map_rx_causes()
1195 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw() local
1198 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1199 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1200 iwl_write_umac_prph(trans, UREG_CHICK, in iwl_pcie_conf_msix_hw()
1209 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1210 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); in iwl_pcie_conf_msix_hw()
1219 iwl_pcie_map_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1221 iwl_pcie_map_non_rx_causes(trans); in iwl_pcie_conf_msix_hw()
1226 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix() local
1233 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1235 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1239 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) in _iwl_trans_pcie_stop_device() argument
1241 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_stop_device()
1251 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1254 iwl_pcie_disable_ict(trans); in _iwl_trans_pcie_stop_device()
1263 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1264 IWL_DEBUG_INFO(trans, in _iwl_trans_pcie_stop_device()
1267 iwl_pcie_synchronize_irqs(trans); in _iwl_trans_pcie_stop_device()
1268 iwl_pcie_rx_napi_sync(trans); in _iwl_trans_pcie_stop_device()
1269 iwl_pcie_tx_stop(trans); in _iwl_trans_pcie_stop_device()
1270 iwl_pcie_rx_stop(trans); in _iwl_trans_pcie_stop_device()
1273 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1274 iwl_write_prph(trans, APMG_CLK_DIS_REG, in _iwl_trans_pcie_stop_device()
1281 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in _iwl_trans_pcie_stop_device()
1282 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1285 iwl_clear_bit(trans, CSR_GP_CNTRL, in _iwl_trans_pcie_stop_device()
1289 iwl_pcie_apm_stop(trans, false); in _iwl_trans_pcie_stop_device()
1292 iwl_trans_pcie_sw_reset(trans, true); in _iwl_trans_pcie_stop_device()
1310 iwl_disable_interrupts(trans); in _iwl_trans_pcie_stop_device()
1313 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1314 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1315 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1321 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_stop_device()
1324 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) in iwl_pcie_synchronize_irqs() argument
1326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_synchronize_irqs()
1338 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, in iwl_trans_pcie_start_fw() argument
1341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_fw()
1346 if (iwl_pcie_prepare_card_hw(trans)) { in iwl_trans_pcie_start_fw()
1347 IWL_WARN(trans, "Exit HW not ready\n"); in iwl_trans_pcie_start_fw()
1351 iwl_enable_rfkill_int(trans); in iwl_trans_pcie_start_fw()
1353 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1360 iwl_disable_interrupts(trans); in iwl_trans_pcie_start_fw()
1363 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_start_fw()
1368 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1376 IWL_WARN(trans, in iwl_trans_pcie_start_fw()
1383 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1384 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, in iwl_trans_pcie_start_fw()
1388 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); in iwl_trans_pcie_start_fw()
1390 ret = iwl_pcie_nic_init(trans); in iwl_trans_pcie_start_fw()
1392 IWL_ERR(trans, "Unable to init nic\n"); in iwl_trans_pcie_start_fw()
1403 iwl_enable_fw_load_int(trans); in iwl_trans_pcie_start_fw()
1406 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1407 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); in iwl_trans_pcie_start_fw()
1410 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1411 ret = iwl_pcie_load_given_ucode_8000(trans, fw); in iwl_trans_pcie_start_fw()
1413 ret = iwl_pcie_load_given_ucode(trans, fw); in iwl_trans_pcie_start_fw()
1416 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); in iwl_trans_pcie_start_fw()
1425 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) in iwl_trans_pcie_fw_alive() argument
1427 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_fw_alive()
1428 iwl_pcie_tx_start(trans, scd_addr); in iwl_trans_pcie_fw_alive()
1431 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, in iwl_trans_pcie_handle_stop_rfkill() argument
1448 hw_rfkill = iwl_is_rfkill_set(trans); in iwl_trans_pcie_handle_stop_rfkill()
1450 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1451 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1453 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1454 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1457 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); in iwl_trans_pcie_handle_stop_rfkill()
1460 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) in iwl_trans_pcie_stop_device() argument
1462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_stop_device()
1465 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1471 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1472 _iwl_trans_pcie_stop_device(trans, false); in iwl_trans_pcie_stop_device()
1473 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); in iwl_trans_pcie_stop_device()
1477 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) in iwl_trans_pcie_rf_kill() argument
1480 IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rf_kill()
1484 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", in iwl_trans_pcie_rf_kill()
1486 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { in iwl_trans_pcie_rf_kill()
1487 if (trans->trans_cfg->gen2) in iwl_trans_pcie_rf_kill()
1488 _iwl_trans_pcie_gen2_stop_device(trans); in iwl_trans_pcie_rf_kill()
1490 _iwl_trans_pcie_stop_device(trans, from_irq); in iwl_trans_pcie_rf_kill()
1494 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, in iwl_pcie_d3_complete_suspend() argument
1497 iwl_disable_interrupts(trans); in iwl_pcie_d3_complete_suspend()
1506 iwl_pcie_disable_ict(trans); in iwl_pcie_d3_complete_suspend()
1508 iwl_pcie_synchronize_irqs(trans); in iwl_pcie_d3_complete_suspend()
1510 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_pcie_d3_complete_suspend()
1512 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); in iwl_pcie_d3_complete_suspend()
1520 iwl_trans_pcie_tx_reset(trans); in iwl_pcie_d3_complete_suspend()
1523 iwl_pcie_set_pwr(trans, true); in iwl_pcie_d3_complete_suspend()
1526 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) in iwl_pcie_d3_handshake() argument
1528 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_d3_handshake()
1531 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) in iwl_pcie_d3_handshake()
1532 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, in iwl_pcie_d3_handshake()
1535 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_d3_handshake()
1536 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, in iwl_pcie_d3_handshake()
1549 IWL_ERR(trans, "Timeout %s D3\n", in iwl_pcie_d3_handshake()
1557 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, in iwl_trans_pcie_d3_suspend() argument
1564 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, in iwl_trans_pcie_d3_suspend()
1567 ret = iwl_pcie_d3_handshake(trans, true); in iwl_trans_pcie_d3_suspend()
1571 iwl_pcie_d3_complete_suspend(trans, test, reset); in iwl_trans_pcie_d3_suspend()
1576 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, in iwl_trans_pcie_d3_resume() argument
1580 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_d3_resume()
1585 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1591 iwl_set_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1594 ret = iwl_finish_nic_init(trans); in iwl_trans_pcie_d3_resume()
1607 iwl_pcie_reset_ict(trans); in iwl_trans_pcie_d3_resume()
1608 iwl_enable_interrupts(trans); in iwl_trans_pcie_d3_resume()
1610 iwl_pcie_set_pwr(trans, false); in iwl_trans_pcie_d3_resume()
1613 iwl_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_d3_resume()
1616 iwl_trans_pcie_tx_reset(trans); in iwl_trans_pcie_d3_resume()
1618 ret = iwl_pcie_rx_init(trans); in iwl_trans_pcie_d3_resume()
1620 IWL_ERR(trans, in iwl_trans_pcie_d3_resume()
1626 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", in iwl_trans_pcie_d3_resume()
1627 iwl_read_umac_prph(trans, WFPM_GP2)); in iwl_trans_pcie_d3_resume()
1629 val = iwl_read32(trans, CSR_RESET); in iwl_trans_pcie_d3_resume()
1637 ret = iwl_pcie_d3_handshake(trans, false); in iwl_trans_pcie_d3_resume()
1644 struct iwl_trans *trans, in iwl_pcie_set_interrupt_capa() argument
1647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_set_interrupt_capa()
1666 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1673 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1685 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1689 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1692 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1695 IWL_DEBUG_INFO(trans, in iwl_pcie_set_interrupt_capa()
1697 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1699 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1718 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) in iwl_pcie_irq_set_affinity() argument
1721 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_pcie_irq_set_affinity()
1724 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1736 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1766 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1772 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1777 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) in iwl_trans_pcie_clear_persistence_bit() argument
1781 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1792 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); in iwl_trans_pcie_clear_persistence_bit()
1794 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); in iwl_trans_pcie_clear_persistence_bit()
1797 IWL_ERR(trans, in iwl_trans_pcie_clear_persistence_bit()
1801 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, in iwl_trans_pcie_clear_persistence_bit()
1808 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) in iwl_pcie_gen2_force_power_gating() argument
1812 ret = iwl_finish_nic_init(trans); in iwl_pcie_gen2_force_power_gating()
1816 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1819 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1823 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, in iwl_pcie_gen2_force_power_gating()
1826 return iwl_trans_pcie_sw_reset(trans, true); in iwl_pcie_gen2_force_power_gating()
1829 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) in _iwl_trans_pcie_start_hw() argument
1831 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in _iwl_trans_pcie_start_hw()
1836 err = iwl_pcie_prepare_card_hw(trans); in _iwl_trans_pcie_start_hw()
1838 IWL_ERR(trans, "Error while preparing HW: %d\n", err); in _iwl_trans_pcie_start_hw()
1842 err = iwl_trans_pcie_clear_persistence_bit(trans); in _iwl_trans_pcie_start_hw()
1846 err = iwl_trans_pcie_sw_reset(trans, true); in _iwl_trans_pcie_start_hw()
1850 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1851 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1852 err = iwl_pcie_gen2_force_power_gating(trans); in _iwl_trans_pcie_start_hw()
1857 err = iwl_pcie_apm_init(trans); in _iwl_trans_pcie_start_hw()
1864 iwl_enable_rfkill_int(trans); in _iwl_trans_pcie_start_hw()
1872 iwl_pcie_check_hw_rf_kill(trans); in _iwl_trans_pcie_start_hw()
1877 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) in iwl_trans_pcie_start_hw() argument
1879 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_start_hw()
1883 ret = _iwl_trans_pcie_start_hw(trans); in iwl_trans_pcie_start_hw()
1889 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) in iwl_trans_pcie_op_mode_leave() argument
1891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_op_mode_leave()
1896 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1898 iwl_pcie_apm_stop(trans, true); in iwl_trans_pcie_op_mode_leave()
1900 iwl_disable_interrupts(trans); in iwl_trans_pcie_op_mode_leave()
1902 iwl_pcie_disable_ict(trans); in iwl_trans_pcie_op_mode_leave()
1906 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_op_mode_leave()
1909 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) in iwl_trans_pcie_write8() argument
1911 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1914 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) in iwl_trans_pcie_write32() argument
1916 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1919 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) in iwl_trans_pcie_read32() argument
1921 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1924 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) in iwl_trans_pcie_prph_msk() argument
1926 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1932 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) in iwl_trans_pcie_read_prph() argument
1934 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_read_prph()
1936 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, in iwl_trans_pcie_read_prph()
1938 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); in iwl_trans_pcie_read_prph()
1941 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_prph() argument
1944 u32 mask = iwl_trans_pcie_prph_msk(trans); in iwl_trans_pcie_write_prph()
1946 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, in iwl_trans_pcie_write_prph()
1948 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); in iwl_trans_pcie_write_prph()
1951 static void iwl_trans_pcie_configure(struct iwl_trans *trans, in iwl_trans_pcie_configure() argument
1954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_configure()
1957 iwl_pcie_free_rbs_pool(trans); in iwl_trans_pcie_configure()
1959 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1960 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1961 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; in iwl_trans_pcie_configure()
1962 trans->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1963 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1964 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; in iwl_trans_pcie_configure()
1980 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1983 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1986 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1987 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
2023 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) in iwl_pcie_free_invalid_tx_cmd() argument
2025 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); in iwl_pcie_free_invalid_tx_cmd()
2028 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) in iwl_pcie_alloc_invalid_tx_cmd() argument
2039 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, in iwl_pcie_alloc_invalid_tx_cmd()
2043 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); in iwl_pcie_alloc_invalid_tx_cmd()
2047 void iwl_trans_pcie_free(struct iwl_trans *trans) in iwl_trans_pcie_free() argument
2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_free()
2052 iwl_pcie_synchronize_irqs(trans); in iwl_trans_pcie_free()
2054 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
2055 iwl_txq_gen2_tx_free(trans); in iwl_trans_pcie_free()
2057 iwl_pcie_tx_free(trans); in iwl_trans_pcie_free()
2058 iwl_pcie_rx_free(trans); in iwl_trans_pcie_free()
2074 iwl_pcie_free_ict(trans); in iwl_trans_pcie_free()
2077 iwl_pcie_free_invalid_tx_cmd(trans); in iwl_trans_pcie_free()
2079 iwl_pcie_free_fw_monitor(trans); in iwl_trans_pcie_free()
2082 trans->dev); in iwl_trans_pcie_free()
2084 trans->dev); in iwl_trans_pcie_free()
2087 iwl_trans_free(trans); in iwl_trans_pcie_free()
2090 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) in iwl_trans_pcie_set_pmi() argument
2093 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
2095 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
2125 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) in iwl_trans_pcie_remove() argument
2129 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_remove()
2132 IWL_ERR(trans, "Device gone - scheduling removal!\n"); in iwl_trans_pcie_remove()
2141 IWL_ERR(trans, in iwl_trans_pcie_remove()
2155 set_bit(STATUS_TRANS_DEAD, &trans->status); in iwl_trans_pcie_remove()
2157 removal->pdev = to_pci_dev(trans->dev); in iwl_trans_pcie_remove()
2169 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) in __iwl_trans_pcie_grab_nic_access() argument
2172 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in __iwl_trans_pcie_grab_nic_access()
2183 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2190 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); in __iwl_trans_pcie_grab_nic_access()
2191 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2214 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); in __iwl_trans_pcie_grab_nic_access()
2216 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); in __iwl_trans_pcie_grab_nic_access()
2222 iwl_trans_pcie_dump_regs(trans); in __iwl_trans_pcie_grab_nic_access()
2225 iwl_trans_pcie_remove(trans, false); in __iwl_trans_pcie_grab_nic_access()
2227 iwl_write32(trans, CSR_RESET, in __iwl_trans_pcie_grab_nic_access()
2243 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) in iwl_trans_pcie_grab_nic_access() argument
2248 ret = __iwl_trans_pcie_grab_nic_access(trans); in iwl_trans_pcie_grab_nic_access()
2257 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) in iwl_trans_pcie_release_nic_access() argument
2259 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_release_nic_access()
2271 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_release_nic_access()
2272 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
2275 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, in iwl_trans_pcie_release_nic_access()
2287 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_read_mem() argument
2298 if (iwl_trans_grab_nic_access(trans)) { in iwl_trans_pcie_read_mem()
2299 iwl_write32(trans, HBUS_TARG_MEM_RADDR, in iwl_trans_pcie_read_mem()
2303 vals[offs] = iwl_read32(trans, in iwl_trans_pcie_read_mem()
2312 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_read_mem()
2324 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, in iwl_trans_pcie_write_mem() argument
2330 if (iwl_trans_grab_nic_access(trans)) { in iwl_trans_pcie_write_mem()
2331 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); in iwl_trans_pcie_write_mem()
2333 iwl_write32(trans, HBUS_TARG_MEM_WDAT, in iwl_trans_pcie_write_mem()
2335 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_write_mem()
2342 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, in iwl_trans_pcie_read_config32() argument
2345 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2349 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) in iwl_trans_pcie_block_txq_ptrs() argument
2353 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { in iwl_trans_pcie_block_txq_ptrs()
2354 struct iwl_txq *txq = trans->txqs.txq[i]; in iwl_trans_pcie_block_txq_ptrs()
2356 if (i == trans->txqs.cmd.q_id) in iwl_trans_pcie_block_txq_ptrs()
2364 iwl_write32(trans, HBUS_TARG_WRPTR, in iwl_trans_pcie_block_txq_ptrs()
2377 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, in iwl_trans_pcie_rxq_dma_data() argument
2380 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_rxq_dma_data()
2382 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2393 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) in iwl_trans_pcie_wait_txq_empty() argument
2401 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2404 if (!test_bit(txq_idx, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2407 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2408 txq = trans->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2443 IWL_ERR(trans, in iwl_trans_pcie_wait_txq_empty()
2445 iwl_txq_log_scd_error(trans, txq); in iwl_trans_pcie_wait_txq_empty()
2449 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); in iwl_trans_pcie_wait_txq_empty()
2454 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) in iwl_trans_pcie_wait_txqs_empty() argument
2461 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2464 if (cnt == trans->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2466 if (!test_bit(cnt, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2471 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); in iwl_trans_pcie_wait_txqs_empty()
2479 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, in iwl_trans_pcie_set_bits_mask() argument
2482 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_set_bits_mask()
2485 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); in iwl_trans_pcie_set_bits_mask()
2523 void iwl_pcie_dump_csr(struct iwl_trans *trans) in iwl_pcie_dump_csr() argument
2552 IWL_ERR(trans, "CSR values:\n"); in iwl_pcie_dump_csr()
2553 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " in iwl_pcie_dump_csr()
2556 IWL_ERR(trans, " %25s: 0X%08x\n", in iwl_pcie_dump_csr()
2558 iwl_read32(trans, csr_tbl[i])); in iwl_pcie_dump_csr()
2565 debugfs_create_file(#name, mode, parent, trans, \
2593 struct iwl_trans *trans; member
2605 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2623 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2638 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show() local
2639 struct iwl_txq *txq = trans->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2643 !!test_bit(state->pos, trans->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2644 !!test_bit(state->pos, trans->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2654 if (state->pos == trans->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2678 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2686 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read() local
2687 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rx_queue_read()
2692 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2701 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2717 u32 r = iwl_get_closed_rb_stts(trans, rxq); in iwl_dbgfs_rx_queue_read()
2735 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read() local
2736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_read()
2793 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write() local
2794 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_interrupt_write()
2812 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write() local
2814 iwl_pcie_dump_csr(trans); in iwl_dbgfs_csr_write()
2823 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read() local
2827 ret = iwl_dump_fh(trans, &buf); in iwl_dbgfs_fh_reg_read()
2841 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read() local
2842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_read()
2848 !(iwl_read32(trans, CSR_GP_CNTRL) & in iwl_dbgfs_rfkill_read()
2858 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write() local
2859 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rfkill_write()
2868 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
2871 iwl_pcie_handle_rfkill_irq(trans, false); in iwl_dbgfs_rfkill_write()
2879 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open() local
2880 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_open()
2882 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
2883 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
2884 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); in iwl_dbgfs_monitor_data_open()
2928 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read() local
2929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_monitor_data_read()
2930 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
2936 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
2938 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
2939 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
2945 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
2956 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); in iwl_dbgfs_monitor_data_read()
2957 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); in iwl_dbgfs_monitor_data_read()
2969 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2987 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
2991 IWL_WARN(trans, in iwl_dbgfs_monitor_data_read()
3011 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read() local
3012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_dbgfs_rf_read()
3044 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) in iwl_trans_pcie_dbgfs_register() argument
3046 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
3058 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) in iwl_trans_pcie_debugfs_cleanup() argument
3060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_debugfs_cleanup()
3069 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) in iwl_trans_pcie_get_cmdlen() argument
3074 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
3075 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); in iwl_trans_pcie_get_cmdlen()
3080 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, in iwl_trans_pcie_dump_rbs() argument
3084 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_rbs()
3092 r = iwl_get_closed_rb_stts(trans, rxq); in iwl_trans_pcie_dump_rbs()
3100 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
3120 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, in iwl_trans_pcie_dump_csr() argument
3132 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_dump_csr()
3139 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, in iwl_trans_pcie_fh_regs_dump() argument
3146 if (!iwl_trans_grab_nic_access(trans)) in iwl_trans_pcie_fh_regs_dump()
3153 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3156 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); in iwl_trans_pcie_fh_regs_dump()
3158 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3159 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); in iwl_trans_pcie_fh_regs_dump()
3161 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, in iwl_trans_pcie_fh_regs_dump()
3164 iwl_trans_release_nic_access(trans); in iwl_trans_pcie_fh_regs_dump()
3172 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, in iwl_trans_pci_dump_marbh_monitor() argument
3180 if (!iwl_trans_grab_nic_access(trans)) in iwl_trans_pci_dump_marbh_monitor()
3183 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); in iwl_trans_pci_dump_marbh_monitor()
3185 buffer[i] = iwl_read_umac_prph_no_grab(trans, in iwl_trans_pci_dump_marbh_monitor()
3187 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); in iwl_trans_pci_dump_marbh_monitor()
3189 iwl_trans_release_nic_access(trans); in iwl_trans_pci_dump_marbh_monitor()
3195 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, in iwl_trans_pcie_dump_pointers() argument
3200 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3205 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3206 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3207 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3208 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3215 write_ptr_val = iwl_read_prph(trans, write_ptr); in iwl_trans_pcie_dump_pointers()
3217 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); in iwl_trans_pcie_dump_pointers()
3219 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_pointers()
3220 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3222 cpu_to_le32(iwl_read_prph(trans, base_high)); in iwl_trans_pcie_dump_pointers()
3231 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, in iwl_trans_pcie_dump_monitor() argument
3235 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3238 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3240 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3241 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3247 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); in iwl_trans_pcie_dump_monitor()
3253 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3259 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3260 base = (iwl_read_prph(trans, base) & in iwl_trans_pcie_dump_monitor()
3262 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3264 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3266 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_monitor()
3267 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3270 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3272 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3274 iwl_trans_pci_dump_marbh_monitor(trans, in iwl_trans_pcie_dump_monitor()
3289 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) in iwl_trans_get_fw_monitor_len() argument
3291 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3294 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3295 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3296 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3299 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3300 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3301 cfg_reg = iwl_read_prph(trans, cfg_reg); in iwl_trans_get_fw_monitor_len()
3303 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3305 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3309 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3312 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3313 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3315 base = iwl_read_prph(trans, base) << in iwl_trans_get_fw_monitor_len()
3316 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3317 end = iwl_read_prph(trans, end) << in iwl_trans_get_fw_monitor_len()
3318 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3321 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3323 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3324 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3336 iwl_trans_pcie_dump_data(struct iwl_trans *trans, in iwl_trans_pcie_dump_data() argument
3341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_dump_data()
3343 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data()
3348 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3349 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3366 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); in iwl_trans_pcie_dump_data()
3374 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3376 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3377 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); in iwl_trans_pcie_dump_data()
3388 num_rbs = iwl_get_closed_rb_stts(trans, rxq); in iwl_trans_pcie_dump_data()
3396 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3397 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3400 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3410 u16 tfd_size = trans->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3421 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3426 cmdlen = iwl_trans_pcie_get_cmdlen(trans, in iwl_trans_pcie_dump_data()
3444 ptr = iwl_txq_dec_wrap(trans, ptr); in iwl_trans_pcie_dump_data()
3454 len += iwl_trans_pcie_dump_csr(trans, &data); in iwl_trans_pcie_dump_data()
3456 len += iwl_trans_pcie_fh_regs_dump(trans, &data); in iwl_trans_pcie_dump_data()
3458 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); in iwl_trans_pcie_dump_data()
3461 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3463 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3465 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3472 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3479 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); in iwl_trans_pcie_dump_data()
3486 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) in iwl_trans_pci_interrupts() argument
3489 iwl_enable_interrupts(trans); in iwl_trans_pci_interrupts()
3491 iwl_disable_interrupts(trans); in iwl_trans_pci_interrupts()
3494 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) in iwl_trans_pcie_sync_nmi() argument
3497 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_sync_nmi()
3501 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sync_nmi()
3510 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); in iwl_trans_pcie_sync_nmi()
3594 struct iwl_trans *trans; in iwl_trans_pcie_alloc() local
3606 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, in iwl_trans_pcie_alloc()
3608 if (!trans) in iwl_trans_pcie_alloc()
3611 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_alloc()
3613 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3646 addr_size = trans->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3682 iwl_disable_interrupts(trans); in iwl_trans_pcie_alloc()
3684 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3685 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3698 trans->hw_rev_step = trans->hw_rev & 0xF; in iwl_trans_pcie_alloc()
3700 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; in iwl_trans_pcie_alloc()
3702 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3704 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); in iwl_trans_pcie_alloc()
3705 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3706 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3711 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); in iwl_trans_pcie_alloc()
3720 ret = iwl_pcie_alloc_ict(trans); in iwl_trans_pcie_alloc()
3727 IRQF_SHARED, DRV_NAME, trans); in iwl_trans_pcie_alloc()
3729 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3739 iwl_dbg_tlv_init(trans); in iwl_trans_pcie_alloc()
3741 return trans; in iwl_trans_pcie_alloc()
3744 iwl_pcie_free_ict(trans); in iwl_trans_pcie_alloc()
3748 iwl_trans_free(trans); in iwl_trans_pcie_alloc()
3752 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, in iwl_trans_pcie_copy_imr_fh() argument
3755 iwl_write_prph(trans, IMR_UREG_CHICK, in iwl_trans_pcie_copy_imr_fh()
3756 iwl_read_prph(trans, IMR_UREG_CHICK) | in iwl_trans_pcie_copy_imr_fh()
3758 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); in iwl_trans_pcie_copy_imr_fh()
3759 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, in iwl_trans_pcie_copy_imr_fh()
3761 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, in iwl_trans_pcie_copy_imr_fh()
3763 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); in iwl_trans_pcie_copy_imr_fh()
3764 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, in iwl_trans_pcie_copy_imr_fh()
3770 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, in iwl_trans_pcie_copy_imr() argument
3773 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); in iwl_trans_pcie_copy_imr()
3777 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); in iwl_trans_pcie_copy_imr()
3782 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); in iwl_trans_pcie_copy_imr()
3783 iwl_trans_pcie_dump_regs(trans); in iwl_trans_pcie_copy_imr()