Lines Matching +full:exported +full:- +full:sram
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
24 #include "iwl-drv.h"
26 #include "iwl-context-info.h"
47 * @invalid: rxb is in driver ownership - not owned by HW
62 * struct isr_statistics - interrupt statistics
80 * struct iwl_rx_transfer_desc - transfer descriptor
94 * struct iwl_rx_completion_desc - completion descriptor
108 * struct iwl_rx_completion_desc_bz - Bz completion descriptor
120 * struct iwl_rxq - Rx queue
123 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
130 * @free_count: Number of pre-allocated buffers in rx_free
139 * @queue: actual rx queue. Not used for multi-rx queue.
168 * struct iwl_rb_allocator - Rx allocator
190 * iwl_get_closed_rb_stts - get closed rb stts from different structs
191 * @rxq - the rxq to get the rb stts from
196 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_get_closed_rb_stts()
197 __le16 *rb_stts = rxq->rb_stts; in iwl_get_closed_rb_stts()
201 struct iwl_rb_status *rb_stts = rxq->rb_stts; in iwl_get_closed_rb_stts()
203 return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF; in iwl_get_closed_rb_stts()
209 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
225 * enum iwl_shared_irq_flags - level of sharing for irq
235 * enum iwl_image_response_code - image response values
274 * enum wl_pcie_imr_status - imr dma transfer state
288 * struct iwl_trans_pcie - PCIe transport specific data
308 * @scd_base_addr: scheduler sram base address in SRAM
313 * @pci_dev: basic pci-network driver stuff
317 * @cmd_queue - command queue number
328 * @msix_entries: array of MSI-X entries
329 * @msix_enabled: true if managed to enable MSI-X
451 return (void *)trans->trans_specific; in IWL_TRANS_GET_PCIE_TRANS()
460 * re-enabled by clearing this bit. This register is defined as in iwl_pcie_clear_irq()
509 * ICT - interrupt handling
551 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_disable_interrupts()
552 if (!trans_pcie->msix_enabled) { in _iwl_disable_interrupts()
563 trans_pcie->fh_init_mask); in _iwl_disable_interrupts()
565 trans_pcie->hw_init_mask); in _iwl_disable_interrupts()
575 while (start < fw->num_sec && in iwl_pcie_get_num_sections()
576 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && in iwl_pcie_get_num_sections()
577 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { in iwl_pcie_get_num_sections()
587 struct iwl_self_init_dram *dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_fw_img()
590 if (!dram->fw) { in iwl_pcie_ctxt_info_free_fw_img()
591 WARN_ON(dram->fw_cnt); in iwl_pcie_ctxt_info_free_fw_img()
595 for (i = 0; i < dram->fw_cnt; i++) in iwl_pcie_ctxt_info_free_fw_img()
596 dma_free_coherent(trans->dev, dram->fw[i].size, in iwl_pcie_ctxt_info_free_fw_img()
597 dram->fw[i].block, dram->fw[i].physical); in iwl_pcie_ctxt_info_free_fw_img()
599 kfree(dram->fw); in iwl_pcie_ctxt_info_free_fw_img()
600 dram->fw_cnt = 0; in iwl_pcie_ctxt_info_free_fw_img()
601 dram->fw = NULL; in iwl_pcie_ctxt_info_free_fw_img()
608 spin_lock_bh(&trans_pcie->irq_lock); in iwl_disable_interrupts()
610 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_disable_interrupts()
618 set_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_enable_interrupts()
619 if (!trans_pcie->msix_enabled) { in _iwl_enable_interrupts()
620 trans_pcie->inta_mask = CSR_INI_SET_MASK; in _iwl_enable_interrupts()
621 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in _iwl_enable_interrupts()
627 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in _iwl_enable_interrupts()
628 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in _iwl_enable_interrupts()
630 ~trans_pcie->fh_mask); in _iwl_enable_interrupts()
632 ~trans_pcie->hw_mask); in _iwl_enable_interrupts()
640 spin_lock_bh(&trans_pcie->irq_lock); in iwl_enable_interrupts()
642 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_enable_interrupts()
649 trans_pcie->hw_mask = msk; in iwl_enable_hw_int_msk_msix()
657 trans_pcie->fh_mask = msk; in iwl_enable_fh_int_msk_msix()
665 if (!trans_pcie->msix_enabled) { in iwl_enable_fw_load_int()
666 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; in iwl_enable_fw_load_int()
667 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int()
670 trans_pcie->hw_init_mask); in iwl_enable_fw_load_int()
682 if (!trans_pcie->msix_enabled) { in iwl_enable_fw_load_int_ctx_info()
690 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; in iwl_enable_fw_load_int_ctx_info()
691 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_fw_load_int_ctx_info()
699 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); in iwl_enable_fw_load_int_ctx_info()
706 if (trans_p->shared_vec_mask) { in queue_name()
707 int vec = trans_p->shared_vec_mask & in queue_name()
719 if (i == trans_p->alloc_vecs - 1) in queue_name()
731 if (!trans_pcie->msix_enabled) { in iwl_enable_rfkill_int()
732 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; in iwl_enable_rfkill_int()
733 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); in iwl_enable_rfkill_int()
736 trans_pcie->fh_init_mask); in iwl_enable_rfkill_int()
741 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { in iwl_enable_rfkill_int()
743 * On 9000-series devices this bit isn't enabled by default, so in iwl_enable_rfkill_int()
745 * to wake up the PCI-E bus for RF-kill interrupts. in iwl_enable_rfkill_int()
758 lockdep_assert_held(&trans_pcie->mutex); in iwl_is_rfkill_set()
760 if (trans_pcie->debug_rfkill == 1) in iwl_is_rfkill_set()
796 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); in iwl_pcie_dbg_on()
828 /* transport gen 2 exported functions */