intel/iwlegacy/4965.h

85  * @scd_retry: (1) Indicates queue will be used in aggregation mode
264  *     1) EEPROM
270  * 1)  Regulatory information (max txpower and channel usage flags) is provided
279  *     sub-bands of contiguous channels.  2.4GHz has just one sub-band,
280  *     but 5 GHz has several sub-bands.
282  *     In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
291  * 1)  Temperature calculation parameters.
299  * 1)  Current values for temperature param R4.
307  * 1)  Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
320  *     Backoff values below are in 1/2 dB units (equivalent to steps in
388  *     txpower is reached.  Each step in the gain table is 1/2 dB.
405  *     2.4 GHz all channels:  3.5 degrees per half-dB step
406  *     5 GHz channels 34-43:  4.5 degrees per half-dB step
407  *     5 GHz channels >= 44:  4.0 degrees per half-dB step
445  *     Group 0:  5 GHz channel 34-43
446  *     Group 1:  5 GHz channel 44-70
447  *     Group 2:  5 GHz channel 71-124
448  *     Group 3:  5 GHz channel 125-200
449  *     Group 4:  2.4 GHz all channels
465  *     bits [3:2], 1 = B, 2 = C.
471  * 10) Select the gain table, based on band (2.4 vs 5 GHz).
487  * Each step is 1/2 dB.
499  * bits [3:2], 1 = B, 2 = C.
516  * Each entry in the gain tables represents a step of 1/2 dB.  Note that these
523  * 1)  DSP gain (or sometimes called DSP attenuation).  This is a fine-grained
534  * There are separate tables for 2.4 GHz and 5 GHz bands.  The 5 GHz table
537  * present during factory calibration).  A 5 Ghz EEPROM idx of "40"
544  * 2.4 GHz gain table
548  *   1        104         0x3f
649  * 5 GHz gain table
660  *  -1        110         0x3D
662  *   1         98         0x3D
814 /* Group 0, 5.2 GHz ch 34-43:  4.5 degrees per 1/2 dB. */
818 /* Group 1, 5.3 GHz ch 44-70:  4.0 degrees per 1/2 dB. */
822 /* Group 2, 5.5 GHz ch 71-124:  4.0 degrees per 1/2 dB. */
826 /* Group 3, 5.7 GHz ch 125-200:  4.0 degrees per 1/2 dB. */
830 /* Group 4, 2.4 GHz all channels:  3.5 degrees per 1/2 dB. */
831 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
836 	CALIB_CH_GROUP_2 = 1,
973  * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
979  * 1)  Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
981  *     Each entry (1 dword) points to a receive buffer (RB) of consistent size
1013  * "read" idx has advanced past 1!  See below).
1024  * corresponding to the "read" idx.  For example, if "read" idx becomes "1",
1055  *  11-0:  Index of driver's most recent prepared-to-be-filled RBD, + 1.
1084  *        typical value 0x10 (about 1/2 msec)
1125  *  24:  1 = Channel 0 is idle
1168  *     3: Enable internal DMA requests (1, normal operation), disable (0)
1220  * 31-24:  1 = Channel buffers empty (channel 7:0)
1221  * 23-16:  1 = No pending requests (channel 7:0)
1231  *	uCode/driver must write "1" in order to clear this flag
1233  *	uCode/driver must write "1" in order to clear this flag
1237  *	uCode/driver must write "1" in order to clear this flag
1243  *	uCode/driver must write "1" in order to clear this flag
1247 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)