318 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)  in ipw_write_reg32()  function
874 		ipw_write_reg32(priv, IPW_EVENT_REG, led);  in ipw_led_link_on()
914 		ipw_write_reg32(priv, IPW_EVENT_REG, led);  in ipw_led_link_off()
958 		ipw_write_reg32(priv, IPW_EVENT_REG, led);  in __ipw_led_activity_on()
1000 		ipw_write_reg32(priv, IPW_EVENT_REG, led);  in ipw_led_activity_off()
1049 	ipw_write_reg32(priv, IPW_EVENT_REG, led);  in ipw_led_band_on()
1072 	ipw_write_reg32(priv, IPW_EVENT_REG, led);  in ipw_led_band_off()
1607 	ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);  in command_event_reg_store()
1630 	ipw_write_reg32(p, 0x301100, reg);  in mem_gpio_reg_store()
2569 	ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);  in eeprom_write_reg()
2727 	ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);  in ipw_fw_dma_enable()
2741 	ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);  in ipw_fw_dma_abort()
2781 	ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);  in ipw_fw_dma_kick()
3052 	ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);  in ipw_load_ucode()
3054 	ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);  in ipw_load_ucode()
3058 	ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);  in ipw_load_ucode()
3061 	ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);  in ipw_load_ucode()
6091 	ipw_write_reg32(priv, reg, *(u32 *) & fr);  in ipw_set_fixed_rate()