Lines Matching +full:0 +full:x422
27 #define RX_FIFO 0 /* data and ctl frames */
31 #define TX_AC_BK_FIFO 0 /* Background TX FIFO */
41 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
109 u32 PAD[3]; /* 0x0 - 0x8 */
110 u32 biststatus; /* 0xC */
111 u32 biststatus2; /* 0x10 */
112 u32 PAD; /* 0x14 */
113 u32 gptimer; /* 0x18 */
114 u32 usectimer; /* 0x1c *//* for corerev >= 26 */
116 /* Interrupt Control *//* 0x20 */
119 u32 PAD[40]; /* 0x60 - 0xFC */
121 u32 intrcvlazy[4]; /* 0x100 - 0x10C */
123 u32 PAD[4]; /* 0x110 - 0x11c */
125 u32 maccontrol; /* 0x120 */
126 u32 maccommand; /* 0x124 */
127 u32 macintstatus; /* 0x128 */
128 u32 macintmask; /* 0x12C */
131 u32 tplatewrptr; /* 0x130 */
132 u32 tplatewrdata; /* 0x134 */
133 u32 PAD[2]; /* 0x138 - 0x13C */
136 union pmqreg pmqreg; /* 0x140 */
137 u32 pmqpatl; /* 0x144 */
138 u32 pmqpath; /* 0x148 */
139 u32 PAD; /* 0x14C */
141 u32 chnstatus; /* 0x150 */
142 u32 psmdebug; /* 0x154 */
143 u32 phydebug; /* 0x158 */
144 u32 machwcap; /* 0x15C */
147 u32 objaddr; /* 0x160 */
148 u32 objdata; /* 0x164 */
149 u32 PAD[2]; /* 0x168 - 0x16c */
151 u32 frmtxstatus; /* 0x170 */
152 u32 frmtxstatus2; /* 0x174 */
153 u32 PAD[2]; /* 0x178 - 0x17c */
156 u32 tsf_timerlow; /* 0x180 */
157 u32 tsf_timerhigh; /* 0x184 */
158 u32 tsf_cfprep; /* 0x188 */
159 u32 tsf_cfpstart; /* 0x18c */
160 u32 tsf_cfpmaxdur32; /* 0x190 */
161 u32 PAD[3]; /* 0x194 - 0x19c */
163 u32 maccontrol1; /* 0x1a0 */
164 u32 machwcap1; /* 0x1a4 */
165 u32 PAD[14]; /* 0x1a8 - 0x1dc */
168 u32 clk_ctl_st; /* 0x1e0 */
173 u32 PAD[5]; /* 0x1ec - 0x1fc */
175 /* 0x200-0x37F dma/pio registers */
179 struct dma32diag dmafifo; /* 0x380 - 0x38C */
181 u32 aggfifocnt; /* 0x390 */
182 u32 aggfifodata; /* 0x394 */
183 u32 PAD[16]; /* 0x398 - 0x3d4 */
184 u16 radioregaddr; /* 0x3d8 */
185 u16 radioregdata; /* 0x3da */
191 u32 rfdisabledly; /* 0x3DC */
194 u16 phyversion; /* 0x3e0 - 0x0 */
195 u16 phybbconfig; /* 0x3e2 - 0x1 */
196 u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
197 u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
198 u16 phyrxstatus0; /* 0x3e8 - 0x4 */
199 u16 phyrxstatus1; /* 0x3ea - 0x5 */
200 u16 phycrsth; /* 0x3ec - 0x6 */
201 u16 phytxerror; /* 0x3ee - 0x7 */
202 u16 phychannel; /* 0x3f0 - 0x8 */
203 u16 PAD[1]; /* 0x3f2 - 0x9 */
204 u16 phytest; /* 0x3f4 - 0xa */
205 u16 phy4waddr; /* 0x3f6 - 0xb */
206 u16 phy4wdatahi; /* 0x3f8 - 0xc */
207 u16 phy4wdatalo; /* 0x3fa - 0xd */
208 u16 phyregaddr; /* 0x3fc - 0xe */
209 u16 phyregdata; /* 0x3fe - 0xf */
211 /* IHR *//* 0x400 - 0x7FE */
214 u16 PAD[3]; /* 0x400 - 0x406 */
215 u16 rcv_fifo_ctl; /* 0x406 */
216 u16 PAD; /* 0x408 - 0x40a */
217 u16 rcv_frm_cnt; /* 0x40a */
218 u16 PAD[4]; /* 0x40a - 0x414 */
219 u16 rssi; /* 0x414 */
220 u16 PAD[5]; /* 0x414 - 0x420 */
221 u16 rcm_ctl; /* 0x420 */
222 u16 rcm_mat_data; /* 0x422 */
223 u16 rcm_mat_mask; /* 0x424 */
224 u16 rcm_mat_dly; /* 0x426 */
225 u16 rcm_cond_mask_l; /* 0x428 */
226 u16 rcm_cond_mask_h; /* 0x42A */
227 u16 rcm_cond_dly; /* 0x42C */
228 u16 PAD[1]; /* 0x42E */
229 u16 ext_ihr_addr; /* 0x430 */
230 u16 ext_ihr_data; /* 0x432 */
231 u16 rxe_phyrs_2; /* 0x434 */
232 u16 rxe_phyrs_3; /* 0x436 */
233 u16 phy_mode; /* 0x438 */
234 u16 rcmta_ctl; /* 0x43a */
235 u16 rcmta_size; /* 0x43c */
236 u16 rcmta_addr0; /* 0x43e */
237 u16 rcmta_addr1; /* 0x440 */
238 u16 rcmta_addr2; /* 0x442 */
239 u16 PAD[30]; /* 0x444 - 0x480 */
241 /* PSM Block *//* 0x480 - 0x500 */
243 u16 PAD; /* 0x480 */
244 u16 psm_maccontrol_h; /* 0x482 */
245 u16 psm_macintstatus_l; /* 0x484 */
246 u16 psm_macintstatus_h; /* 0x486 */
247 u16 psm_macintmask_l; /* 0x488 */
248 u16 psm_macintmask_h; /* 0x48A */
249 u16 PAD; /* 0x48C */
250 u16 psm_maccommand; /* 0x48E */
251 u16 psm_brc; /* 0x490 */
252 u16 psm_phy_hdr_param; /* 0x492 */
253 u16 psm_postcard; /* 0x494 */
254 u16 psm_pcard_loc_l; /* 0x496 */
255 u16 psm_pcard_loc_h; /* 0x498 */
256 u16 psm_gpio_in; /* 0x49A */
257 u16 psm_gpio_out; /* 0x49C */
258 u16 psm_gpio_oe; /* 0x49E */
260 u16 psm_bred_0; /* 0x4A0 */
261 u16 psm_bred_1; /* 0x4A2 */
262 u16 psm_bred_2; /* 0x4A4 */
263 u16 psm_bred_3; /* 0x4A6 */
264 u16 psm_brcl_0; /* 0x4A8 */
265 u16 psm_brcl_1; /* 0x4AA */
266 u16 psm_brcl_2; /* 0x4AC */
267 u16 psm_brcl_3; /* 0x4AE */
268 u16 psm_brpo_0; /* 0x4B0 */
269 u16 psm_brpo_1; /* 0x4B2 */
270 u16 psm_brpo_2; /* 0x4B4 */
271 u16 psm_brpo_3; /* 0x4B6 */
272 u16 psm_brwk_0; /* 0x4B8 */
273 u16 psm_brwk_1; /* 0x4BA */
274 u16 psm_brwk_2; /* 0x4BC */
275 u16 psm_brwk_3; /* 0x4BE */
277 u16 psm_base_0; /* 0x4C0 */
278 u16 psm_base_1; /* 0x4C2 */
279 u16 psm_base_2; /* 0x4C4 */
280 u16 psm_base_3; /* 0x4C6 */
281 u16 psm_base_4; /* 0x4C8 */
282 u16 psm_base_5; /* 0x4CA */
283 u16 psm_base_6; /* 0x4CC */
284 u16 psm_pc_reg_0; /* 0x4CE */
285 u16 psm_pc_reg_1; /* 0x4D0 */
286 u16 psm_pc_reg_2; /* 0x4D2 */
287 u16 psm_pc_reg_3; /* 0x4D4 */
288 u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
289 u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
290 u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
292 /* TXE0 Block *//* 0x500 - 0x580 */
293 u16 txe_ctl; /* 0x500 */
294 u16 txe_aux; /* 0x502 */
295 u16 txe_ts_loc; /* 0x504 */
296 u16 txe_time_out; /* 0x506 */
297 u16 txe_wm_0; /* 0x508 */
298 u16 txe_wm_1; /* 0x50A */
299 u16 txe_phyctl; /* 0x50C */
300 u16 txe_status; /* 0x50E */
301 u16 txe_mmplcp0; /* 0x510 */
302 u16 txe_mmplcp1; /* 0x512 */
303 u16 txe_phyctl1; /* 0x514 */
305 u16 PAD[0x05]; /* 0x510 - 0x51E */
308 u16 xmtfifodef; /* 0x520 */
309 u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
310 u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
311 u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
312 u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
313 u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
314 u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
316 u16 PAD[0x09]; /* 0x52E - 0x53E */
318 u16 xmtfifocmd; /* 0x540 */
319 u16 xmtfifoflush; /* 0x542 */
320 u16 xmtfifothresh; /* 0x544 */
321 u16 xmtfifordy; /* 0x546 */
322 u16 xmtfifoprirdy; /* 0x548 */
323 u16 xmtfiforqpri; /* 0x54A */
324 u16 xmttplatetxptr; /* 0x54C */
325 u16 PAD; /* 0x54E */
326 u16 xmttplateptr; /* 0x550 */
327 u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
328 u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
329 u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
330 u16 PAD[0x04]; /* 0x558 - 0x55E */
331 u16 xmttplatedatalo; /* 0x560 */
332 u16 xmttplatedatahi; /* 0x562 */
334 u16 PAD[2]; /* 0x564 - 0x566 */
336 u16 xmtsel; /* 0x568 */
337 u16 xmttxcnt; /* 0x56A */
338 u16 xmttxshmaddr; /* 0x56C */
340 u16 PAD[0x09]; /* 0x56E - 0x57E */
343 u16 PAD[0x40]; /* 0x580 - 0x5FE */
346 u16 PAD[0X02]; /* 0x600 - 0x602 */
347 u16 tsf_cfpstrt_l; /* 0x604 */
348 u16 tsf_cfpstrt_h; /* 0x606 */
349 u16 PAD[0X05]; /* 0x608 - 0x610 */
350 u16 tsf_cfppretbtt; /* 0x612 */
351 u16 PAD[0XD]; /* 0x614 - 0x62C */
352 u16 tsf_clk_frac_l; /* 0x62E */
353 u16 tsf_clk_frac_h; /* 0x630 */
354 u16 PAD[0X14]; /* 0x632 - 0x658 */
355 u16 tsf_random; /* 0x65A */
356 u16 PAD[0x05]; /* 0x65C - 0x664 */
358 u16 tsf_gpt2_stat; /* 0x666 */
359 u16 tsf_gpt2_ctr_l; /* 0x668 */
360 u16 tsf_gpt2_ctr_h; /* 0x66A */
361 u16 tsf_gpt2_val_l; /* 0x66C */
362 u16 tsf_gpt2_val_h; /* 0x66E */
363 u16 tsf_gptall_stat; /* 0x670 */
364 u16 PAD[0x07]; /* 0x672 - 0x67E */
367 u16 ifs_sifs_rx_tx_tx; /* 0x680 */
368 u16 ifs_sifs_nav_tx; /* 0x682 */
369 u16 ifs_slot; /* 0x684 */
370 u16 PAD; /* 0x686 */
371 u16 ifs_ctl; /* 0x688 */
372 u16 PAD[0x3]; /* 0x68a - 0x68F */
373 u16 ifsstat; /* 0x690 */
374 u16 ifsmedbusyctl; /* 0x692 */
375 u16 iftxdur; /* 0x694 */
376 u16 PAD[0x3]; /* 0x696 - 0x69b */
378 u16 ifs_aifsn; /* 0x69c */
379 u16 ifs_ctl1; /* 0x69e */
382 u16 scc_ctl; /* 0x6a0 */
383 u16 scc_timer_l; /* 0x6a2 */
384 u16 scc_timer_h; /* 0x6a4 */
385 u16 scc_frac; /* 0x6a6 */
386 u16 scc_fastpwrup_dly; /* 0x6a8 */
387 u16 scc_per; /* 0x6aa */
388 u16 scc_per_frac; /* 0x6ac */
389 u16 scc_cal_timer_l; /* 0x6ae */
390 u16 scc_cal_timer_h; /* 0x6b0 */
391 u16 PAD; /* 0x6b2 */
393 u16 PAD[0x26];
396 u16 nav_ctl; /* 0x700 */
397 u16 navstat; /* 0x702 */
398 u16 PAD[0x3e]; /* 0x702 - 0x77E */
400 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
401 u16 PAD[0x20]; /* 0x780 - 0x7BE */
403 u16 wepctl; /* 0x7C0 */
404 u16 wepivloc; /* 0x7C2 */
405 u16 wepivkey; /* 0x7C4 */
406 u16 wepwkey; /* 0x7C6 */
408 u16 PAD[4]; /* 0x7C8 - 0x7CE */
409 u16 pcmctl; /* 0X7D0 */
410 u16 pcmstat; /* 0X7D2 */
411 u16 PAD[6]; /* 0x7D4 - 0x7DE */
413 u16 pmqctl; /* 0x7E0 */
414 u16 pmqstatus; /* 0x7E2 */
415 u16 pmqpat0; /* 0x7E4 */
416 u16 pmqpat1; /* 0x7E6 */
417 u16 pmqpat2; /* 0x7E8 */
419 u16 pmqdat; /* 0x7EA */
420 u16 pmqdator; /* 0x7EC */
421 u16 pmqhst; /* 0x7EE */
422 u16 pmqpath0; /* 0x7F0 */
423 u16 pmqpath1; /* 0x7F2 */
424 u16 pmqpath2; /* 0x7F4 */
425 u16 pmqdath; /* 0x7F6 */
427 u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
429 /* SHM *//* 0x800 - 0xEFE */
430 u16 PAD[0x380]; /* 0x800 - 0xEFE */
436 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */
453 #define IRL_TO_MASK 0x00ffffff /* timeout */
454 #define IRL_FC_MASK 0xff000000 /* frame count */
480 #define MCTL_EN_MAC (1 << 0)
483 #define MCMD_BCN0VLD (1 << 0)
493 #define MI_MACSSPNDD (1 << 0)
550 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
554 #define PMQH_DATA_MASK 0xffff0000
556 #define PMQH_BSSCFG 0x00100000
558 #define PMQH_PMOFF 0x00010000
560 #define PMQH_PMON 0x00020000
562 #define PMQH_DASAT 0x00040000
564 #define PMQH_ATIMFAIL 0x00080000
566 #define PMQH_DEL_ENTRY 0x00000001
568 #define PMQH_DEL_MULT 0x00000002
570 #define PMQH_OFLO 0x00000004
572 #define PMQH_NOT_EMPTY 0x00000008
576 #define PDBG_CRS (1 << 0)
595 #define OBJADDR_SEL_MASK 0x000F0000
596 #define OBJADDR_UCM_SEL 0x00000000
597 #define OBJADDR_SHM_SEL 0x00010000
598 #define OBJADDR_SCR_SEL 0x00020000
599 #define OBJADDR_IHR_SEL 0x00030000
600 #define OBJADDR_RCMTA_SEL 0x00040000
601 #define OBJADDR_SRCHM_SEL 0x00060000
602 #define OBJADDR_WINC 0x01000000
603 #define OBJADDR_RINC 0x02000000
604 #define OBJADDR_AUTO_INC 0x03000000
606 #define WEP_PCMADDR 0x07d4
607 #define WEP_PCMDATA 0x07d6
610 #define TXS_V (1 << 0) /* valid bit */
611 #define TXS_STATUS_MASK 0xffff
612 #define TXS_FID_MASK 0xffff0000
616 #define TXS_SEQ_MASK 0xffff
617 #define TXS_PTX_MASK 0xff0000
619 #define TXS_MU_MASK 0x01000000
623 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
624 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
625 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
626 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
629 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
630 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
633 #define CFPREP_CBI_MASK 0xffffffc0
635 #define CFPREP_CFPP 0x00000001
649 #define PV_AV_MASK 0xf000
653 #define PV_PT_MASK 0x0f00
657 #define PV_PV_MASK 0x000f
665 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
677 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
678 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
679 #define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
680 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
681 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
685 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
687 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
691 (((length) & 0x0fff) << 5))
693 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
727 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
728 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
729 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */
735 plcp[1] = len & 0xff; \
736 plcp[2] = ((len >> 8) & 0xff); \
737 } while (0)
752 __le16 MacTxControlLow; /* 0x0 */
753 __le16 MacTxControlHigh; /* 0x1 */
754 __le16 MacFrameControl; /* 0x2 */
755 __le16 TxFesTimeNormal; /* 0x3 */
756 __le16 PhyTxControlWord; /* 0x4 */
757 __le16 PhyTxControlWord_1; /* 0x5 */
758 __le16 PhyTxControlWord_1_Fbr; /* 0x6 */
759 __le16 PhyTxControlWord_1_Rts; /* 0x7 */
760 __le16 PhyTxControlWord_1_FbrRts; /* 0x8 */
761 __le16 MainRates; /* 0x9 */
762 __le16 XtraFrameTypes; /* 0xa */
763 u8 IV[16]; /* 0x0b - 0x12 */
764 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
765 __le16 TxFesTimeFallback; /* 0x16 */
766 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
767 __le16 RTSDurFallback; /* 0x1a */
768 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
769 __le16 FragDurFallback; /* 0x1e */
770 __le16 MModeLen; /* 0x1f */
771 __le16 MModeFbrLen; /* 0x20 */
772 __le16 TstampLow; /* 0x21 */
773 __le16 TstampHigh; /* 0x22 */
774 __le16 ABI_MimoAntSel; /* 0x23 */
775 __le16 PreloadSize; /* 0x24 */
776 __le16 AmpduSeqCtl; /* 0x25 */
777 __le16 TxFrameID; /* 0x26 */
778 __le16 TxStatus; /* 0x27 */
779 __le16 MaxNMpdus; /* 0x28 */
780 __le16 MaxABytes_MRT; /* 0x29 */
781 __le16 MaxABytes_FBR; /* 0x2a */
782 __le16 MinMBytes; /* 0x2b */
783 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
784 struct ieee80211_rts rts_frame; /* 0x2f - 0x36 */
785 u16 PAD; /* 0x37 */
791 #define FT_CCK 0
801 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
807 #define TXC_AMIC 0x8000
808 #define TXC_SENDCTS 0x0800
809 #define TXC_AMPDU_MASK 0x0600
810 #define TXC_BW_40 0x0100
811 #define TXC_FREQBAND_5G 0x0080
812 #define TXC_DFCS 0x0040
813 #define TXC_IGNOREPMQ 0x0020
814 #define TXC_HWSEQ 0x0010
815 #define TXC_STARTMSDU 0x0008
816 #define TXC_SENDRTS 0x0004
817 #define TXC_LONGFRAME 0x0002
818 #define TXC_IMMEDACK 0x0001
821 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
822 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000
823 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
824 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000
828 * 0 = LONG for CCK/MM for MIMO
830 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000
834 #define TXC_AMPDU_FBR 0x1000
835 #define TXC_SECKEY_MASK 0x0FF0
838 #define TXC_ALT_TXPWR 0x0008
839 #define TXC_SECTYPE_MASK 0x0007
840 #define TXC_SECTYPE_SHIFT 0
846 #define PHY_TXC_PWR_MASK 0xFC00
848 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
850 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
851 #define PHY_TXC_LCNPHY_ANT_LAST 0x0000
852 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
853 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
854 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
855 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
856 #define PHY_TXC_SHORT_HDR 0x0010
858 #define PHY_TXC_OLD_ANT_0 0x0000
859 #define PHY_TXC_OLD_ANT_1 0x0100
860 #define PHY_TXC_OLD_ANT_LAST 0x0300
863 #define PHY_TXC1_BW_MASK 0x0007
864 #define PHY_TXC1_BW_10MHZ 0
871 #define PHY_TXC1_MODE_MASK 0x0038
872 #define PHY_TXC1_MODE_SISO 0
878 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bits 6-13 */
886 #define PHY_AWS_ANTDIV 0x2000
897 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
899 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
901 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
918 #define TX_STATUS_FRM_RTX_MASK 0xF000
920 #define TX_STATUS_RTS_RTX_MASK 0x0F00
922 #define TX_STATUS_MASK 0x00FE
926 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
929 #define TX_STATUS_VALID (1 << 0) /* Tx status valid */
930 #define TX_STATUS_NO_ACK 0
943 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
948 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
951 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
952 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
953 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
959 #define RCM_INC_MASK_H 0x0080
960 #define RCM_INC_MASK_L 0x0040
961 #define RCM_INC_DATA 0x0020
962 #define RCM_INDEX_MASK 0x001F
965 #define RCM_MAC_OFFSET 0 /* current MAC address */
987 #define WKEY_SEL_MASK 0x1F
994 #define M_ADDR_BMP_BLK (0x37e * 2)
997 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
1018 #define SKL_ALGO_MASK 0x0007
1019 #define SKL_ALGO_SHIFT 0
1020 #define SKL_KEYID_MASK 0x0008
1022 #define SKL_INDEX_MASK 0x03F0
1024 #define SKL_GRP_ALGO_MASK 0x1c00
1028 #define SKL_IBSS_INDEX_MASK 0x01F0
1030 #define SKL_IBSS_KEYID1_MASK 0x0600
1032 #define SKL_IBSS_KEYID2_MASK 0x1800
1034 #define SKL_IBSS_KEYALGO_MASK 0xE000
1037 #define WSEC_MODE_OFF 0
1041 #define WSEC_ALGO_OFF 0
1049 #define AES_MODE_NONE 0
1052 /* WEP_CTL (Rev 0) */
1053 #define WECR0_KEYREG_SHIFT 0
1054 #define WECR0_KEYREG_MASK 0x7
1058 #define WECR0_WEPALG_MASK (0x7 << 5)
1060 #define WECR0_WKEYSEL_MASK (0x7 << 8)
1066 #define T_ACTS_TPL_BASE (0)
1067 #define T_NULL_TPL_BASE (0xc * 2)
1068 #define T_QNULL_TPL_BASE (0x1c * 2)
1069 #define T_RR_TPL_BASE (0x2c * 2)
1070 #define T_BCN0_TPL_BASE (0x34 * 2)
1071 #define T_PRS_TPL_BASE (0x134 * 2)
1072 #define T_BCN1_TPL_BASE (0x234 * 2)
1083 #define M_MACHW_VER (0x00b * 2)
1086 #define M_MACHW_CAP_L (0x060 * 2)
1087 #define M_MACHW_CAP_H (0x061 * 2)
1090 #define M_EDCF_STATUS_OFF (0x007 * 2)
1091 #define M_TXF_CUR_INDEX (0x018 * 2)
1092 #define M_EDCF_QINFO (0x120 * 2)
1095 #define M_DOT11_SLOT (0x008 * 2)
1096 #define M_DOT11_DTIMPERIOD (0x009 * 2)
1097 #define M_NOSLPZNATDTIM (0x026 * 2)
1100 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1101 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1102 #define M_BCN_TXTSF_OFFSET (0x00e * 2)
1103 #define M_TIMBPOS_INBEACON (0x00f * 2)
1104 #define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1105 #define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1106 #define M_BCN_PCTLWD (0x02a * 2)
1107 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1110 #define M_MAXRXFRM_LEN (0x010 * 2)
1113 #define M_RSP_PCTLWD (0x011 * 2)
1116 #define M_TXPWR_N (0x012 * 2)
1117 #define M_TXPWR_TARGET (0x013 * 2)
1118 #define M_TXPWR_MAX (0x014 * 2)
1119 #define M_TXPWR_CUR (0x019 * 2)
1122 #define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1125 #define M_SEC_DEFIVLOC (0x01e * 2)
1126 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1127 #define M_PHYVER (0x028 * 2)
1128 #define M_PHYTYPE (0x029 * 2)
1129 #define M_SECRXKEYS_PTR (0x02b * 2)
1130 #define M_TKMICKEYS_PTR (0x059 * 2)
1131 #define M_SECKINDXALGO_BLK (0x2ea * 2)
1133 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1134 #define M_TKIP_TSC_TTAK (0x18c * 2)
1137 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1140 #define M_SSIDLEN (0x024 * 2)
1141 #define M_PRB_RESP_FRM_LEN (0x025 * 2)
1142 #define M_PRS_MAXTIME (0x03a * 2)
1143 #define M_SSID (0xb0 * 2)
1144 #define M_CTXPRS_BLK (0xc0 * 2)
1145 #define C_CTX_PCTLWD_POS (0x4 * 2)
1148 #define M_OFDM_OFFSET (0x027 * 2)
1151 #define M_B_TSSI_0 (0x02c * 2)
1152 #define M_B_TSSI_1 (0x02d * 2)
1155 #define M_HOST_FLAGS1 (0x02f * 2)
1156 #define M_HOST_FLAGS2 (0x030 * 2)
1157 #define M_HOST_FLAGS3 (0x031 * 2)
1158 #define M_HOST_FLAGS4 (0x03c * 2)
1159 #define M_HOST_FLAGS5 (0x06a * 2)
1162 #define M_RADAR_REG (0x033 * 2)
1165 #define M_A_TSSI_0 (0x034 * 2)
1166 #define M_A_TSSI_1 (0x035 * 2)
1169 #define M_NOISE_IF_COUNT (0x034 * 2)
1170 #define M_NOISE_IF_TIMEOUT (0x035 * 2)
1172 #define M_RF_RX_SP_REG1 (0x036 * 2)
1175 #define M_G_TSSI_0 (0x038 * 2)
1176 #define M_G_TSSI_1 (0x039 * 2)
1179 #define M_JSSI_0 (0x44 * 2)
1180 #define M_JSSI_1 (0x45 * 2)
1181 #define M_JSSI_AUX (0x46 * 2)
1183 #define M_CUR_2050_RADIOCODE (0x47 * 2)
1186 #define M_FIFOSIZE0 (0x4c * 2)
1187 #define M_FIFOSIZE1 (0x4d * 2)
1188 #define M_FIFOSIZE2 (0x4e * 2)
1189 #define M_FIFOSIZE3 (0x4f * 2)
1193 #define M_CURCHANNEL (0x50 * 2)
1194 #define D11_CURCHANNEL_5G 0x0100;
1195 #define D11_CURCHANNEL_40 0x0200;
1196 #define D11_CURCHANNEL_MAX 0x00FF;
1199 #define M_BCMC_FID (0x54 * 2)
1200 #define INVALIDFID 0xffff
1203 #define M_BCN_PCTL1WD (0x058 * 2)
1206 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1207 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1210 #define M_LCN_RSSI_0 0x1332
1211 #define M_LCN_RSSI_1 0x1338
1212 #define M_LCN_RSSI_2 0x133e
1213 #define M_LCN_RSSI_3 0x1344
1216 #define M_LCN_SNR_A_0 0x1334
1217 #define M_LCN_SNR_B_0 0x1336
1219 #define M_LCN_SNR_A_1 0x133a
1220 #define M_LCN_SNR_B_1 0x133c
1222 #define M_LCN_SNR_A_2 0x1340
1223 #define M_LCN_SNR_B_2 0x1342
1225 #define M_LCN_SNR_A_3 0x1346
1226 #define M_LCN_SNR_B_3 0x1348
1231 #define M_LCNPHY_DSC_TIME (0x98d*2)
1232 #define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1233 #define M_LCNPHY_RESET_CNT (0x98c*2)
1236 #define M_RT_DIRMAP_A (0xe0 * 2)
1237 #define M_RT_BBRSMAP_A (0xf0 * 2)
1238 #define M_RT_DIRMAP_B (0x100 * 2)
1239 #define M_RT_BBRSMAP_B (0x110 * 2)
1246 #define M_20IN40_IQ (0x380 * 2)
1249 #define M_CURR_IDX1 (0x384 * 2)
1250 #define M_CURR_IDX2 (0x387 * 2)
1252 #define M_BSCALE_ANT0 (0x5e * 2)
1253 #define M_BSCALE_ANT1 (0x5f * 2)
1256 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1257 #define M_ANTSEL_CLKDIV (0x61 * 2)
1258 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1260 #define M_MIMO_MAXSYM (0x5d * 2)
1261 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1262 #define MIMO_MAXSYM_MAX 0xffff /* 64k */
1264 #define M_WATCHDOG_8TU (0x1e * 2)
1270 #define M_PKTENG_CTRL (0x6c * 2)
1272 #define M_PKTENG_IFS (0x6d * 2)
1274 #define M_PKTENG_FRMCNT_LO (0x6e * 2)
1276 #define M_PKTENG_FRMCNT_HI (0x6f * 2)
1279 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1280 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1283 #define M_PKTENG_MODE_TX 0x0001
1284 #define M_PKTENG_MODE_TX_RIFS 0x0004
1285 #define M_PKTENG_MODE_TX_CTS 0x0008
1286 #define M_PKTENG_MODE_RX 0x0002
1287 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1288 #define M_PKTENG_MODE_MASK 0x0003
1290 #define M_PKTENG_FRMCNT_VLD 0x0100
1294 #define M_SMPL_COL_BMP (0x37d * 2)
1296 #define M_SMPL_COL_CTL (0x3b2 * 2)
1299 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1300 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1302 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1321 #define MHF1 0 /* Hostflag 1 index */
1329 #define MHF1_ANTDIV 0x0001
1331 #define MHF1_EDCF 0x0100
1332 #define MHF1_IQSWAP_WAR 0x0200
1334 #define MHF1_FORCEFASTCLK 0x0400
1339 #define MHF2_TXBCMC_NOW 0x0040
1341 #define MHF2_HWPWRCTL 0x0080
1342 #define MHF2_NPHY40MHZ_WAR 0x0800
1346 #define MHF3_ANTSEL_EN 0x0001
1347 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1348 #define MHF3_ANTSEL_MODE 0x0002
1349 #define MHF3_RESERVED1 0x0004
1350 #define MHF3_RESERVED2 0x0008
1351 #define MHF3_NPHY_MLADV_WAR 0x0010
1354 /* force bphy Tx on core 0 (board level WAR) */
1355 #define MHF4_BPHY_TXCORE0 0x0080
1357 #define MHF4_EXTPA_ENABLE 0x4000
1360 #define MHF5_4313_GPIOCTRL 0x0001
1361 #define MHF5_RESERVED1 0x0002
1362 #define MHF5_RESERVED2 0x0004
1364 #define M_RADIO_PWR (0x32 * 2)
1367 #define M_PHY_NOISE (0x037 * 2)
1368 #define PHY_NOISE_MASK 0x00ff
1375 * PhyRxStatus_0: PhyRxStatus 15:0
1418 #define PRXS0_FT_MASK 0x0003
1420 #define PRXS0_CLIP_MASK 0x000C
1423 #define PRXS0_UNSRATE 0x0010
1425 #define PRXS0_RXANT_UPSUBBAND 0x0020
1427 #define PRXS0_LCRS 0x0040
1429 #define PRXS0_SHORTH 0x0080
1431 #define PRXS0_PLCPFV 0x0100
1433 #define PRXS0_PLCPHCF 0x0200
1435 #define PRXS0_GAIN_CTL 0x4000
1437 #define PRXS0_ANTSEL_MASK 0xF000
1438 #define PRXS0_ANTSEL_SHIFT 0x12
1441 #define PRXS0_CCK 0x0000
1443 #define PRXS0_OFDM 0x0001
1444 #define PRXS0_PREN 0x0002
1445 #define PRXS0_STDN 0x0003
1448 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1449 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1450 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1451 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1454 #define PRXS1_JSSI_MASK 0x00FF
1455 #define PRXS1_JSSI_SHIFT 0
1456 #define PRXS1_SQ_MASK 0xFF00
1460 #define PRXS1_nphy_PWR0_MASK 0x00FF
1461 #define PRXS1_nphy_PWR1_MASK 0xFF00
1465 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1466 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1467 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1470 /* core enables for {3..0}, 0=disabled, 1=enabled */
1471 #define PRXS1_HTPHY_CORE_MASK 0x000F
1473 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0
1475 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00
1479 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F
1481 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0
1482 /* Rx power on core 0 */
1483 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00
1487 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF
1489 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00
1493 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF
1495 #define PRXS4_HTPHY_CFO 0xFF00
1499 #define PRXS5_HTPHY_FFO 0x00FF
1501 #define PRXS5_HTPHY_AR 0xFF00
1506 /* Get Rx power on core 0 */
1517 #define RXS_BCNSENT 0x8000
1518 #define RXS_SECKINDX_MASK 0x07e0
1525 #define RXS_FCSERR (1 << 0)
1529 #define RXS_AGGTYPE_MASK 0x6
1532 #define RXS_RXANT_MASK 0x3
1536 #define RXS_CHAN_40 0x1000
1537 #define RXS_CHAN_5G 0x0800
1538 #define RXS_CHAN_ID_MASK 0x07f8
1540 #define RXS_CHAN_PHYTYPE_MASK 0x0007
1541 #define RXS_CHAN_PHYTYPE_SHIFT 0
1544 #define M_PWRIND_BLKS (0x184 * 2)
1545 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1546 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1547 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1548 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1553 #define M_PSM_SOFT_REGS 0x0
1554 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1555 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1556 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1557 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1559 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1560 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1561 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1562 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1563 #define M_PRETBTT (0x4b * 2)
1566 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2))
1567 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1568 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1569 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1572 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1576 #define DBGST_INACTIVE 0
1588 S_RSV0 = 0,
1592 /* offset 0x03: scratch registers for Dot11-contants */
1600 /* offset 0x09: Tx-side scratch registers */
1612 /* offset 0x13: Rx-side scratch registers */
1626 /* offset 0x1B: Receive TSF time stored in SCR */
1634 /* offset 0x21: Scratch pad regs used in microcode as temp storage */
1652 S_REVID4, /* 0x33 */
1653 S_INDX, /* 0x34 */
1654 S_ADDR0, /* 0x35 */
1655 S_ADDR1, /* 0x36 */
1656 S_ADDR2, /* 0x37 */
1657 S_ADDR3, /* 0x38 */
1658 S_ADDR4, /* 0x39 */
1659 S_ADDR5, /* 0x3A */
1660 S_TMP6, /* 0x3B */
1664 S_STREG6, /* 0x3F */
1673 #define SLOW_CTRL_PDE (1 << 0)
1678 u16 txallfrm; /* 0x80 */
1679 u16 txrtsfrm; /* 0x82 */
1680 u16 txctsfrm; /* 0x84 */
1681 u16 txackfrm; /* 0x86 */
1682 u16 txdnlfrm; /* 0x88 */
1683 u16 txbcnfrm; /* 0x8a */
1684 u16 txfunfl[8]; /* 0x8c - 0x9b */
1685 u16 txtplunfl; /* 0x9c */
1686 u16 txphyerr; /* 0x9e */
1687 u16 pktengrxducast; /* 0xa0 */
1688 u16 pktengrxdmcast; /* 0xa2 */
1689 u16 rxfrmtoolong; /* 0xa4 */
1690 u16 rxfrmtooshrt; /* 0xa6 */
1691 u16 rxinvmachdr; /* 0xa8 */
1692 u16 rxbadfcs; /* 0xaa */
1693 u16 rxbadplcp; /* 0xac */
1694 u16 rxcrsglitch; /* 0xae */
1695 u16 rxstrt; /* 0xb0 */
1696 u16 rxdfrmucastmbss; /* 0xb2 */
1697 u16 rxmfrmucastmbss; /* 0xb4 */
1698 u16 rxcfrmucast; /* 0xb6 */
1699 u16 rxrtsucast; /* 0xb8 */
1700 u16 rxctsucast; /* 0xba */
1701 u16 rxackucast; /* 0xbc */
1702 u16 rxdfrmocast; /* 0xbe */
1703 u16 rxmfrmocast; /* 0xc0 */
1704 u16 rxcfrmocast; /* 0xc2 */
1705 u16 rxrtsocast; /* 0xc4 */
1706 u16 rxctsocast; /* 0xc6 */
1707 u16 rxdfrmmcast; /* 0xc8 */
1708 u16 rxmfrmmcast; /* 0xca */
1709 u16 rxcfrmmcast; /* 0xcc */
1710 u16 rxbeaconmbss; /* 0xce */
1711 u16 rxdfrmucastobss; /* 0xd0 */
1712 u16 rxbeaconobss; /* 0xd2 */
1713 u16 rxrsptmout; /* 0xd4 */
1714 u16 bcntxcancl; /* 0xd6 */
1716 u16 rxf0ovfl; /* 0xda */
1717 u16 rxf1ovfl; /* 0xdc */
1718 u16 rxf2ovfl; /* 0xde */
1719 u16 txsfovfl; /* 0xe0 */
1720 u16 pmqovfl; /* 0xe2 */
1721 u16 rxcgprqfrm; /* 0xe4 */
1722 u16 rxcgprsqovfl; /* 0xe6 */
1723 u16 txcgprsfail; /* 0xe8 */
1724 u16 txcgprssuc; /* 0xea */
1725 u16 prs_timeout; /* 0xec */
1730 u16 txburst; /* 0xf6 # tx bursts */
1732 u16 phywatchdog; /* 0xfa # of phy watchdog events */
1738 #define SICF_PCLKE 0x0004 /* PHY clock enable */
1739 #define SICF_PRST 0x0008 /* PHY reset */
1740 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1741 #define SICF_FREF 0x0020 /* PLL FreqRefSelect */
1745 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1746 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1747 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1748 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1749 #define SICF_GMODE 0x2000 /* gmode enable */
1752 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy */
1753 #define SISF_5G_PHY 0x0002 /* 5G capable phy */
1754 #define SISF_FCLKA 0x0004 /* FastClkAvailable */
1755 #define SISF_DB_PHY 0x0008 /* Dualband phy */
1760 #define BPHY_REG_OFT_BASE 0x0
1762 #define BPHY_BB_CONFIG 0x01
1763 #define BPHY_ADCBIAS 0x02
1764 #define BPHY_ANACORE 0x03
1765 #define BPHY_PHYCRSTH 0x06
1766 #define BPHY_TEST 0x0a
1767 #define BPHY_PA_TX_TO 0x10
1768 #define BPHY_SYNTH_DC_TO 0x11
1769 #define BPHY_PA_TX_TIME_UP 0x12
1770 #define BPHY_RX_FLTR_TIME_UP 0x13
1771 #define BPHY_TX_POWER_OVERRIDE 0x14
1772 #define BPHY_RF_OVERRIDE 0x15
1773 #define BPHY_RF_TR_LOOKUP1 0x16
1774 #define BPHY_RF_TR_LOOKUP2 0x17
1775 #define BPHY_COEFFS 0x18
1776 #define BPHY_PLL_OUT 0x19
1777 #define BPHY_REFRESH_MAIN 0x1a
1778 #define BPHY_REFRESH_TO0 0x1b
1779 #define BPHY_REFRESH_TO1 0x1c
1780 #define BPHY_RSSI_TRESH 0x20
1781 #define BPHY_IQ_TRESH_HH 0x21
1782 #define BPHY_IQ_TRESH_H 0x22
1783 #define BPHY_IQ_TRESH_L 0x23
1784 #define BPHY_IQ_TRESH_LL 0x24
1785 #define BPHY_GAIN 0x25
1786 #define BPHY_LNA_GAIN_RANGE 0x26
1787 #define BPHY_JSSI 0x27
1788 #define BPHY_TSSI_CTL 0x28
1789 #define BPHY_TSSI 0x29
1790 #define BPHY_TR_LOSS_CTL 0x2a
1791 #define BPHY_LO_LEAKAGE 0x2b
1792 #define BPHY_LO_RSSI_ACC 0x2c
1793 #define BPHY_LO_IQMAG_ACC 0x2d
1794 #define BPHY_TX_DC_OFF1 0x2e
1795 #define BPHY_TX_DC_OFF2 0x2f
1796 #define BPHY_PEAK_CNT_THRESH 0x30
1797 #define BPHY_FREQ_OFFSET 0x31
1798 #define BPHY_DIVERSITY_CTL 0x32
1799 #define BPHY_PEAK_ENERGY_LO 0x33
1800 #define BPHY_PEAK_ENERGY_HI 0x34
1801 #define BPHY_SYNC_CTL 0x35
1802 #define BPHY_TX_PWR_CTRL 0x36
1803 #define BPHY_TX_EST_PWR 0x37
1804 #define BPHY_STEP 0x38
1805 #define BPHY_WARMUP 0x39
1806 #define BPHY_LMS_CFF_READ 0x3a
1807 #define BPHY_LMS_COEFF_I 0x3b
1808 #define BPHY_LMS_COEFF_Q 0x3c
1809 #define BPHY_SIG_POW 0x3d
1810 #define BPHY_RFDC_CANCEL_CTL 0x3e
1811 #define BPHY_HDR_TYPE 0x40
1812 #define BPHY_SFD_TO 0x41
1813 #define BPHY_SFD_CTL 0x42
1814 #define BPHY_DEBUG 0x43
1815 #define BPHY_RX_DELAY_COMP 0x44
1816 #define BPHY_CRS_DROP_TO 0x45
1817 #define BPHY_SHORT_SFD_NZEROS 0x46
1818 #define BPHY_DSSS_COEFF1 0x48
1819 #define BPHY_DSSS_COEFF2 0x49
1820 #define BPHY_CCK_COEFF1 0x4a
1821 #define BPHY_CCK_COEFF2 0x4b
1822 #define BPHY_TR_CORR 0x4c
1823 #define BPHY_ANGLE_SCALE 0x4d
1824 #define BPHY_TX_PWR_BASE_IDX 0x4e
1825 #define BPHY_OPTIONAL_MODES2 0x4f
1826 #define BPHY_CCK_LMS_STEP 0x50
1827 #define BPHY_BYPASS 0x51
1828 #define BPHY_CCK_DELAY_LONG 0x52
1829 #define BPHY_CCK_DELAY_SHORT 0x53
1830 #define BPHY_PPROC_CHAN_DELAY 0x54
1831 #define BPHY_DDFS_ENABLE 0x58
1832 #define BPHY_PHASE_SCALE 0x59
1833 #define BPHY_FREQ_CONTROL 0x5a
1834 #define BPHY_LNA_GAIN_RANGE_10 0x5b
1835 #define BPHY_LNA_GAIN_RANGE_32 0x5c
1836 #define BPHY_OPTIONAL_MODES 0x5d
1837 #define BPHY_RX_STATUS2 0x5e
1838 #define BPHY_RX_STATUS3 0x5f
1839 #define BPHY_DAC_CONTROL 0x60
1840 #define BPHY_ANA11G_FILT_CTRL 0x62
1841 #define BPHY_REFRESH_CTRL 0x64
1842 #define BPHY_RF_OVERRIDE2 0x65
1843 #define BPHY_SPUR_CANCEL_CTRL 0x66
1844 #define BPHY_FINE_DIGIGAIN_CTRL 0x67
1845 #define BPHY_RSSI_LUT 0x88
1846 #define BPHY_RSSI_LUT_END 0xa7
1847 #define BPHY_TSSI_LUT 0xa8
1848 #define BPHY_TSSI_LUT_END 0xc7
1849 #define BPHY_TSSI2PWR_LUT 0x380
1850 #define BPHY_TSSI2PWR_LUT_END 0x39f
1851 #define BPHY_LOCOMP_LUT 0x3a0
1852 #define BPHY_LOCOMP_LUT_END 0x3bf
1853 #define BPHY_TXGAIN_LUT 0x3c0
1854 #define BPHY_TXGAIN_LUT_END 0x3ff
1857 #define PHY_BBC_ANT_MASK 0x0180
1859 #define BB_DARWIN 0x1000
1860 #define BBCFG_RESETCCA 0x4000
1861 #define BBCFG_RESETRX 0x8000
1863 /* Bits in phytest(0x0a): */
1864 #define TST_DDFS 0x2000
1865 #define TST_TXFILT1 0x0800
1866 #define TST_UNSCRAM 0x0400
1867 #define TST_CARR_SUPP 0x0200
1868 #define TST_DC_COMP_LOOP 0x0100
1869 #define TST_LOOPBACK 0x0080
1870 #define TST_TXFILT0 0x0040
1871 #define TST_TXTEST_ENABLE 0x0020
1872 #define TST_TXTEST_RATE 0x0018
1873 #define TST_TXTEST_PHASE 0x0007
1876 #define TST_TXTEST_RATE_1MBPS 0
1882 #define SHM_BYT_CNT 0x2 /* IHR location */
1883 #define MAX_BYT_CNT 0x600 /* Maximum frame len */