Lines Matching refs:dev
94 static inline bool b43_nphy_ipa(struct b43_wldev *dev) in b43_nphy_ipa() argument
96 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || in b43_nphy_ipa()
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); in b43_nphy_ipa()
102 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) in b43_nphy_get_rx_core_state() argument
104 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> in b43_nphy_get_rx_core_state()
113 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, in b43_nphy_force_rf_sequence() argument
125 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_force_rf_sequence()
129 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_force_rf_sequence()
131 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); in b43_nphy_force_rf_sequence()
133 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) in b43_nphy_force_rf_sequence()
137 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
139 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_force_rf_sequence()
142 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev19() argument
150 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override_rev7() argument
154 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_rev7()
170 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); in b43_nphy_rf_ctl_override_rev7()
174 b43err(dev->wl, "Invalid override value %d\n", override); in b43_nphy_rf_ctl_override_rev7()
183 b43_phy_mask(dev, en_addr, ~en_mask); in b43_nphy_rf_ctl_override_rev7()
185 b43_phy_mask(dev, val_addr, ~e->val_mask); in b43_nphy_rf_ctl_override_rev7()
188 b43_phy_set(dev, en_addr, en_mask); in b43_nphy_rf_ctl_override_rev7()
190 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); in b43_nphy_rf_ctl_override_rev7()
197 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, in b43_nphy_rf_ctl_override_one_to_many() argument
201 struct b43_phy *phy = &dev->phy; in b43_nphy_rf_ctl_override_one_to_many()
208 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
209 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
210 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
213 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
214 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
215 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
216 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
217 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
220 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
221 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
222 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
223 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
227 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
229 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
233 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
235 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
241 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, in b43_nphy_rf_ctl_override() argument
250 if (dev->phy.rev >= 3) { in b43_nphy_rf_ctl_override()
254 b43err(dev->wl, in b43_nphy_rf_ctl_override()
266 b43_phy_mask(dev, en_addr, ~(field)); in b43_nphy_rf_ctl_override()
267 b43_phy_mask(dev, val_addr, in b43_nphy_rf_ctl_override()
271 b43_phy_set(dev, en_addr, field); in b43_nphy_rf_ctl_override()
272 b43_phy_maskset(dev, val_addr, in b43_nphy_rf_ctl_override()
281 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); in b43_nphy_rf_ctl_override()
284 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); in b43_nphy_rf_ctl_override()
289 b43err(dev->wl, in b43_nphy_rf_ctl_override()
304 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), in b43_nphy_rf_ctl_override()
307 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rf_ctl_override()
308 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_override()
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); in b43_nphy_rf_ctl_override()
316 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override_rev7() argument
334 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override_rev7()
335 b43_phy_mask(dev, 0x2ff, ~0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
336 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override_rev7()
339 b43_phy_maskset(dev, reg, ~0xC0, value << 6); in b43_nphy_rf_ctl_intc_override_rev7()
340 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override_rev7()
342 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); in b43_nphy_rf_ctl_intc_override_rev7()
343 b43_phy_set(dev, 0x2ff, 0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
344 b43_phy_set(dev, 0x2ff, 0x0001); in b43_nphy_rf_ctl_intc_override_rev7()
348 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_rf_ctl_intc_override_rev7()
352 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
353 b43_phy_set(dev, reg, 0x1000); in b43_nphy_rf_ctl_intc_override_rev7()
356 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
365 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
366 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
369 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override_rev7()
378 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override_rev7()
379 b43_phy_mask(dev, reg, ~tmp2); in b43_nphy_rf_ctl_intc_override_rev7()
386 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, in b43_nphy_rf_ctl_intc_override() argument
393 if (dev->phy.rev >= 7) { in b43_nphy_rf_ctl_intc_override()
394 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, in b43_nphy_rf_ctl_intc_override()
399 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_rf_ctl_intc_override()
407 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override()
411 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override()
412 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rf_ctl_intc_override()
416 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_rf_ctl_intc_override()
418 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
420 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
423 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { in b43_nphy_rf_ctl_intc_override()
430 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
432 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, in b43_nphy_rf_ctl_intc_override()
435 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_rf_ctl_intc_override()
437 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
439 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rf_ctl_intc_override()
442 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { in b43_nphy_rf_ctl_intc_override()
449 b43err(dev->wl, in b43_nphy_rf_ctl_intc_override()
451 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rf_ctl_intc_override()
456 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
463 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
466 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
473 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
476 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rf_ctl_intc_override()
483 b43_phy_maskset(dev, reg, ~tmp, val); in b43_nphy_rf_ctl_intc_override()
494 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, in b43_nphy_write_clip_detection() argument
497 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); in b43_nphy_write_clip_detection()
498 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); in b43_nphy_write_clip_detection()
502 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) in b43_nphy_read_clip_detection() argument
504 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); in b43_nphy_read_clip_detection()
505 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); in b43_nphy_read_clip_detection()
509 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) in b43_nphy_classifier() argument
513 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
514 b43_mac_suspend(dev); in b43_nphy_classifier()
516 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); in b43_nphy_classifier()
521 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); in b43_nphy_classifier()
523 if (dev->dev->core_rev == 16) in b43_nphy_classifier()
524 b43_mac_enable(dev); in b43_nphy_classifier()
530 static void b43_nphy_reset_cca(struct b43_wldev *dev) in b43_nphy_reset_cca() argument
534 b43_phy_force_clock(dev, 1); in b43_nphy_reset_cca()
535 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_reset_cca()
536 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
538 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); in b43_nphy_reset_cca()
539 b43_phy_force_clock(dev, 0); in b43_nphy_reset_cca()
540 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_reset_cca()
544 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) in b43_nphy_stay_in_carrier_search() argument
546 struct b43_phy *phy = &dev->phy; in b43_nphy_stay_in_carrier_search()
552 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); in b43_nphy_stay_in_carrier_search()
553 b43_nphy_classifier(dev, 0x7, in b43_nphy_stay_in_carrier_search()
555 b43_nphy_read_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
556 b43_nphy_write_clip_detection(dev, clip); in b43_nphy_stay_in_carrier_search()
558 b43_nphy_reset_cca(dev); in b43_nphy_stay_in_carrier_search()
561 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); in b43_nphy_stay_in_carrier_search()
562 b43_nphy_write_clip_detection(dev, nphy->clip_state); in b43_nphy_stay_in_carrier_search()
568 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) in b43_nphy_read_lpf_ctl() argument
571 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; in b43_nphy_read_lpf_ctl()
572 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; in b43_nphy_read_lpf_ctl()
576 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) in b43_nphy_adjust_lna_gain_table() argument
578 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_adjust_lna_gain_table()
588 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_adjust_lna_gain_table()
591 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_adjust_lna_gain_table()
595 tmp = 40370 - 315 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
597 tmp = 23242 - 224 * dev->phy.channel; in b43_nphy_adjust_lna_gain_table()
617 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); in b43_nphy_adjust_lna_gain_table()
622 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, in b43_nphy_adjust_lna_gain_table()
624 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, in b43_nphy_adjust_lna_gain_table()
628 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_adjust_lna_gain_table()
632 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, in b43_nphy_set_rf_sequence() argument
635 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_set_rf_sequence()
637 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; in b43_nphy_set_rf_sequence()
642 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rf_sequence()
644 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); in b43_nphy_set_rf_sequence()
645 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); in b43_nphy_set_rf_sequence()
648 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); in b43_nphy_set_rf_sequence()
649 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); in b43_nphy_set_rf_sequence()
653 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rf_sequence()
660 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, in b43_radio_2057_chantab_upload() argument
665 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
666 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
667 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextal… in b43_radio_2057_chantab_upload()
668 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
669 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
670 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
671 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
672 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
673 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
674 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
675 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
676 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
677 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0… in b43_radio_2057_chantab_upload()
678 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
679 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
680 …b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1… in b43_radio_2057_chantab_upload()
681 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
682 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
685 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); in b43_radio_2057_chantab_upload()
686 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); in b43_radio_2057_chantab_upload()
687 …b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsiz… in b43_radio_2057_chantab_upload()
688 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); in b43_radio_2057_chantab_upload()
689 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); in b43_radio_2057_chantab_upload()
690 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); in b43_radio_2057_chantab_upload()
691 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); in b43_radio_2057_chantab_upload()
692 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); in b43_radio_2057_chantab_upload()
693 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); in b43_radio_2057_chantab_upload()
694 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); in b43_radio_2057_chantab_upload()
695 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); in b43_radio_2057_chantab_upload()
696 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); in b43_radio_2057_chantab_upload()
697 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); in b43_radio_2057_chantab_upload()
698 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); in b43_radio_2057_chantab_upload()
699 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); in b43_radio_2057_chantab_upload()
700 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); in b43_radio_2057_chantab_upload()
701 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); in b43_radio_2057_chantab_upload()
702 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); in b43_radio_2057_chantab_upload()
703 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); in b43_radio_2057_chantab_upload()
704 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); in b43_radio_2057_chantab_upload()
705 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); in b43_radio_2057_chantab_upload()
706 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); in b43_radio_2057_chantab_upload()
707 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); in b43_radio_2057_chantab_upload()
708 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); in b43_radio_2057_chantab_upload()
709 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); in b43_radio_2057_chantab_upload()
710 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); in b43_radio_2057_chantab_upload()
711 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); in b43_radio_2057_chantab_upload()
712 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); in b43_radio_2057_chantab_upload()
716 static void b43_radio_2057_setup(struct b43_wldev *dev, in b43_radio_2057_setup() argument
720 struct b43_phy *phy = &dev->phy; in b43_radio_2057_setup()
722 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); in b43_radio_2057_setup()
727 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2057_setup()
728 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); in b43_radio_2057_setup()
729 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
730 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
731 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
733 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); in b43_radio_2057_setup()
734 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
735 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
736 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
740 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); in b43_radio_2057_setup()
741 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); in b43_radio_2057_setup()
742 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_radio_2057_setup()
743 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); in b43_radio_2057_setup()
744 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); in b43_radio_2057_setup()
746 if (b43_is_40mhz(dev)) { in b43_radio_2057_setup()
749 b43_radio_write(dev, in b43_radio_2057_setup()
752 b43_radio_write(dev, in b43_radio_2057_setup()
759 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); in b43_radio_2057_setup()
760 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
761 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); in b43_radio_2057_setup()
762 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); in b43_radio_2057_setup()
766 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2057_setup()
770 if (b43_nphy_ipa(dev)) { in b43_radio_2057_setup()
784 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, in b43_radio_2057_setup()
787 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, in b43_radio_2057_setup()
790 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, in b43_radio_2057_setup()
793 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, in b43_radio_2057_setup()
800 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); in b43_radio_2057_setup()
801 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); in b43_radio_2057_setup()
802 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); in b43_radio_2057_setup()
803 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); in b43_radio_2057_setup()
810 static u8 b43_radio_2057_rcal(struct b43_wldev *dev) in b43_radio_2057_rcal() argument
812 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rcal()
834 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); in b43_radio_2057_rcal()
836 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); in b43_radio_2057_rcal()
840 b43_phy_write(dev, phy_to_store[i], 0); in b43_radio_2057_rcal()
841 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); in b43_radio_2057_rcal()
842 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); in b43_radio_2057_rcal()
843 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); in b43_radio_2057_rcal()
844 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); in b43_radio_2057_rcal()
845 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); in b43_radio_2057_rcal()
846 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); in b43_radio_2057_rcal()
850 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); in b43_radio_2057_rcal()
852 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
853 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); in b43_radio_2057_rcal()
856 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
857 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
858 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
859 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); in b43_radio_2057_rcal()
862 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
863 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); in b43_radio_2057_rcal()
864 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
865 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
866 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); in b43_radio_2057_rcal()
867 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
872 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); in b43_radio_2057_rcal()
876 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); in b43_radio_2057_rcal()
880 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); in b43_radio_2057_rcal()
883 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { in b43_radio_2057_rcal()
884 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rcal()
887 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; in b43_radio_2057_rcal()
890 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); in b43_radio_2057_rcal()
894 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); in b43_radio_2057_rcal()
896 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); in b43_radio_2057_rcal()
901 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); in b43_radio_2057_rcal()
902 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, in b43_radio_2057_rcal()
906 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); in b43_radio_2057_rcal()
907 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); in b43_radio_2057_rcal()
910 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
913 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
914 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); in b43_radio_2057_rcal()
924 static u16 b43_radio_2057_rccal(struct b43_wldev *dev) in b43_radio_2057_rccal() argument
926 struct b43_phy *phy = &dev->phy; in b43_radio_2057_rccal()
933 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
934 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); in b43_radio_2057_rccal()
936 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
937 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); in b43_radio_2057_rccal()
939 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
942 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
943 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
945 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
947 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
952 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
953 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
955 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
956 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); in b43_radio_2057_rccal()
958 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
962 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
964 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
966 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
968 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
973 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
974 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); in b43_radio_2057_rccal()
975 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
977 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
978 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
979 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); in b43_radio_2057_rccal()
984 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
986 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, in b43_radio_2057_rccal()
988 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rccal()
991 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); in b43_radio_2057_rccal()
993 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
997 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
999 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
1004 static void b43_radio_2057_init_pre(struct b43_wldev *dev) in b43_radio_2057_init_pre() argument
1006 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1008 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1009 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); in b43_radio_2057_init_pre()
1010 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); in b43_radio_2057_init_pre()
1013 static void b43_radio_2057_init_post(struct b43_wldev *dev) in b43_radio_2057_init_post() argument
1015 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); in b43_radio_2057_init_post()
1018 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); in b43_radio_2057_init_post()
1020 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); in b43_radio_2057_init_post()
1021 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); in b43_radio_2057_init_post()
1023 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); in b43_radio_2057_init_post()
1024 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); in b43_radio_2057_init_post()
1026 if (dev->phy.do_full_init) { in b43_radio_2057_init_post()
1027 b43_radio_2057_rcal(dev); in b43_radio_2057_init_post()
1028 b43_radio_2057_rccal(dev); in b43_radio_2057_init_post()
1030 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); in b43_radio_2057_init_post()
1034 static void b43_radio_2057_init(struct b43_wldev *dev) in b43_radio_2057_init() argument
1036 b43_radio_2057_init_pre(dev); in b43_radio_2057_init()
1037 r2057_upload_inittabs(dev); in b43_radio_2057_init()
1038 b43_radio_2057_init_post(dev); in b43_radio_2057_init()
1045 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, in b43_chantab_radio_2056_upload() argument
1048 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); in b43_chantab_radio_2056_upload()
1049 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); in b43_chantab_radio_2056_upload()
1050 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); in b43_chantab_radio_2056_upload()
1051 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); in b43_chantab_radio_2056_upload()
1052 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); in b43_chantab_radio_2056_upload()
1053 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, in b43_chantab_radio_2056_upload()
1055 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, in b43_chantab_radio_2056_upload()
1057 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, in b43_chantab_radio_2056_upload()
1059 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, in b43_chantab_radio_2056_upload()
1061 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, in b43_chantab_radio_2056_upload()
1063 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, in b43_chantab_radio_2056_upload()
1065 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, in b43_chantab_radio_2056_upload()
1067 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, in b43_chantab_radio_2056_upload()
1069 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, in b43_chantab_radio_2056_upload()
1071 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); in b43_chantab_radio_2056_upload()
1072 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); in b43_chantab_radio_2056_upload()
1073 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); in b43_chantab_radio_2056_upload()
1075 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1077 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1080 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1082 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1084 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1086 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1088 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1090 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1097 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, in b43_chantab_radio_2056_upload()
1099 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, in b43_chantab_radio_2056_upload()
1102 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1104 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1106 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1108 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1110 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1112 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, in b43_chantab_radio_2056_upload()
1121 static void b43_radio_2056_setup(struct b43_wldev *dev, in b43_radio_2056_setup() argument
1124 struct b43_phy *phy = &dev->phy; in b43_radio_2056_setup()
1125 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_2056_setup()
1126 enum nl80211_band band = b43_current_band(dev->wl); in b43_radio_2056_setup()
1134 B43_WARN_ON(dev->phy.rev < 3); in b43_radio_2056_setup()
1137 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || in b43_radio_2056_setup()
1138 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || in b43_radio_2056_setup()
1139 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && in b43_radio_2056_setup()
1140 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); in b43_radio_2056_setup()
1142 b43_chantab_radio_2056_upload(dev, e); in b43_radio_2056_setup()
1143 b2056_upload_syn_pll_cp2(dev, band == NL80211_BAND_5GHZ); in b43_radio_2056_setup()
1146 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1147 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1148 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1149 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1150 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1151 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); in b43_radio_2056_setup()
1152 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); in b43_radio_2056_setup()
1154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); in b43_radio_2056_setup()
1155 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); in b43_radio_2056_setup()
1159 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); in b43_radio_2056_setup()
1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); in b43_radio_2056_setup()
1162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); in b43_radio_2056_setup()
1163 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); in b43_radio_2056_setup()
1166 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_radio_2056_setup()
1167 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1169 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); in b43_radio_2056_setup()
1170 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); in b43_radio_2056_setup()
1173 if (dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) { in b43_radio_2056_setup()
1176 if (dev->phy.rev >= 5) { in b43_radio_2056_setup()
1177 b43_radio_write(dev, in b43_radio_2056_setup()
1180 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || in b43_radio_2056_setup()
1181 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { in b43_radio_2056_setup()
1200 b43_radio_write(dev, in b43_radio_2056_setup()
1203 b43_radio_write(dev, in b43_radio_2056_setup()
1206 b43_radio_write(dev, in b43_radio_2056_setup()
1209 b43_radio_write(dev, in b43_radio_2056_setup()
1212 b43_radio_write(dev, in b43_radio_2056_setup()
1215 b43_radio_write(dev, in b43_radio_2056_setup()
1218 b43_radio_write(dev, in b43_radio_2056_setup()
1222 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; in b43_radio_2056_setup()
1223 b43_radio_write(dev, in b43_radio_2056_setup()
1226 b43_radio_write(dev, in b43_radio_2056_setup()
1229 b43_radio_write(dev, in b43_radio_2056_setup()
1233 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); in b43_radio_2056_setup()
1235 } else if (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ) { in b43_radio_2056_setup()
1267 b43_radio_write(dev, in b43_radio_2056_setup()
1269 b43_radio_write(dev, in b43_radio_2056_setup()
1271 b43_radio_write(dev, in b43_radio_2056_setup()
1273 b43_radio_write(dev, in b43_radio_2056_setup()
1275 b43_radio_write(dev, in b43_radio_2056_setup()
1277 b43_radio_write(dev, in b43_radio_2056_setup()
1279 b43_radio_write(dev, in b43_radio_2056_setup()
1281 b43_radio_write(dev, in b43_radio_2056_setup()
1283 b43_radio_write(dev, in b43_radio_2056_setup()
1285 b43_radio_write(dev, in b43_radio_2056_setup()
1292 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); in b43_radio_2056_setup()
1293 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1294 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); in b43_radio_2056_setup()
1295 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1296 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); in b43_radio_2056_setup()
1300 static u8 b43_radio_2056_rcal(struct b43_wldev *dev) in b43_radio_2056_rcal() argument
1302 struct b43_phy *phy = &dev->phy; in b43_radio_2056_rcal()
1308 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); in b43_radio_2056_rcal()
1309 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); in b43_radio_2056_rcal()
1312 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1314 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); in b43_radio_2056_rcal()
1316 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, in b43_radio_2056_rcal()
1318 b43err(dev->wl, "Radio recalibration timeout\n"); in b43_radio_2056_rcal()
1322 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1323 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); in b43_radio_2056_rcal()
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); in b43_radio_2056_rcal()
1326 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); in b43_radio_2056_rcal()
1331 static void b43_radio_init2056_pre(struct b43_wldev *dev) in b43_radio_init2056_pre() argument
1333 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1336 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1338 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1340 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2056_pre()
1344 static void b43_radio_init2056_post(struct b43_wldev *dev) in b43_radio_init2056_post() argument
1346 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); in b43_radio_init2056_post()
1347 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); in b43_radio_init2056_post()
1348 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); in b43_radio_init2056_post()
1350 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); in b43_radio_init2056_post()
1351 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); in b43_radio_init2056_post()
1352 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); in b43_radio_init2056_post()
1353 if (dev->phy.do_full_init) in b43_radio_init2056_post()
1354 b43_radio_2056_rcal(dev); in b43_radio_init2056_post()
1361 static void b43_radio_init2056(struct b43_wldev *dev) in b43_radio_init2056() argument
1363 b43_radio_init2056_pre(dev); in b43_radio_init2056()
1364 b2056_upload_inittabs(dev, 0, 0); in b43_radio_init2056()
1365 b43_radio_init2056_post(dev); in b43_radio_init2056()
1372 static void b43_chantab_radio_upload(struct b43_wldev *dev, in b43_chantab_radio_upload() argument
1375 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); in b43_chantab_radio_upload()
1376 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); in b43_chantab_radio_upload()
1377 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); in b43_chantab_radio_upload()
1378 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); in b43_chantab_radio_upload()
1379 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1381 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); in b43_chantab_radio_upload()
1382 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); in b43_chantab_radio_upload()
1383 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); in b43_chantab_radio_upload()
1384 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); in b43_chantab_radio_upload()
1385 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1387 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); in b43_chantab_radio_upload()
1388 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); in b43_chantab_radio_upload()
1389 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); in b43_chantab_radio_upload()
1390 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); in b43_chantab_radio_upload()
1391 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1393 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); in b43_chantab_radio_upload()
1394 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); in b43_chantab_radio_upload()
1395 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); in b43_chantab_radio_upload()
1396 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); in b43_chantab_radio_upload()
1397 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1399 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); in b43_chantab_radio_upload()
1400 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); in b43_chantab_radio_upload()
1401 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); in b43_chantab_radio_upload()
1402 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); in b43_chantab_radio_upload()
1403 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_chantab_radio_upload()
1405 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); in b43_chantab_radio_upload()
1406 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); in b43_chantab_radio_upload()
1410 static void b43_radio_2055_setup(struct b43_wldev *dev, in b43_radio_2055_setup() argument
1413 B43_WARN_ON(dev->phy.rev >= 3); in b43_radio_2055_setup()
1415 b43_chantab_radio_upload(dev, e); in b43_radio_2055_setup()
1417 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); in b43_radio_2055_setup()
1418 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); in b43_radio_2055_setup()
1419 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ in b43_radio_2055_setup()
1420 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); in b43_radio_2055_setup()
1424 static void b43_radio_init2055_pre(struct b43_wldev *dev) in b43_radio_init2055_pre() argument
1426 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1428 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1431 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_radio_init2055_pre()
1435 static void b43_radio_init2055_post(struct b43_wldev *dev) in b43_radio_init2055_post() argument
1437 struct b43_phy_n *nphy = dev->phy.n; in b43_radio_init2055_post()
1438 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_radio_init2055_post()
1442 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM in b43_radio_init2055_post()
1443 && dev->dev->board_type == SSB_BOARD_CB2_4321 in b43_radio_init2055_post()
1444 && dev->dev->board_rev >= 0x41); in b43_radio_init2055_post()
1449 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); in b43_radio_init2055_post()
1451 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1452 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1454 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); in b43_radio_init2055_post()
1455 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); in b43_radio_init2055_post()
1456 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); in b43_radio_init2055_post()
1457 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); in b43_radio_init2055_post()
1458 b43_radio_set(dev, B2055_CAL_MISC, 0x1); in b43_radio_init2055_post()
1460 b43_radio_set(dev, B2055_CAL_MISC, 0x40); in b43_radio_init2055_post()
1461 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) in b43_radio_init2055_post()
1462 b43err(dev->wl, "radio post init timeout\n"); in b43_radio_init2055_post()
1463 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); in b43_radio_init2055_post()
1464 b43_switch_channel(dev, dev->phy.channel); in b43_radio_init2055_post()
1465 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1466 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1467 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1468 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1469 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1470 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1472 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1473 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1475 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1476 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1485 static void b43_radio_init2055(struct b43_wldev *dev) in b43_radio_init2055() argument
1487 b43_radio_init2055_pre(dev); in b43_radio_init2055()
1488 if (b43_status(dev) < B43_STAT_INITIALIZED) { in b43_radio_init2055()
1490 b2055_upload_inittab(dev, 0, 0); in b43_radio_init2055()
1492 bool ghz5 = b43_current_band(dev->wl) == NL80211_BAND_5GHZ; in b43_radio_init2055()
1493 b2055_upload_inittab(dev, ghz5, 0); in b43_radio_init2055()
1495 b43_radio_init2055_post(dev); in b43_radio_init2055()
1503 static int b43_nphy_load_samples(struct b43_wldev *dev, in b43_nphy_load_samples() argument
1505 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_load_samples()
1511 b43err(dev->wl, "allocation for samples loading failed\n"); in b43_nphy_load_samples()
1515 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_load_samples()
1521 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); in b43_nphy_load_samples()
1525 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_load_samples()
1530 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, in b43_nphy_gen_load_samples() argument
1537 bw = b43_is_40mhz(dev) ? 40 : 20; in b43_nphy_gen_load_samples()
1541 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) in b43_nphy_gen_load_samples()
1546 if (b43_is_40mhz(dev)) in b43_nphy_gen_load_samples()
1554 b43err(dev->wl, "allocation for samples generation failed\n"); in b43_nphy_gen_load_samples()
1567 i = b43_nphy_load_samples(dev, samples, len); in b43_nphy_gen_load_samples()
1573 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, in b43_nphy_run_samples() argument
1577 struct b43_phy *phy = &dev->phy; in b43_nphy_run_samples()
1578 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_run_samples()
1583 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_run_samples()
1588 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; in b43_nphy_run_samples()
1589 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; in b43_nphy_run_samples()
1594 u16 value = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_run_samples()
1596 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, in b43_nphy_run_samples()
1599 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, in b43_nphy_run_samples()
1606 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); in b43_nphy_run_samples()
1611 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; in b43_nphy_run_samples()
1612 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_run_samples()
1615 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); in b43_nphy_run_samples()
1618 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); in b43_nphy_run_samples()
1620 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); in b43_nphy_run_samples()
1622 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); in b43_nphy_run_samples()
1624 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); in b43_nphy_run_samples()
1626 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); in b43_nphy_run_samples()
1628 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_run_samples()
1629 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); in b43_nphy_run_samples()
1632 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); in b43_nphy_run_samples()
1635 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { in b43_nphy_run_samples()
1642 b43err(dev->wl, "run samples timeout\n"); in b43_nphy_run_samples()
1644 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); in b43_nphy_run_samples()
1646 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_run_samples()
1654 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, in b43_nphy_scale_offset_rssi() argument
1669 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1671 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1673 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1675 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); in b43_nphy_scale_offset_rssi()
1679 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1683 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); in b43_nphy_scale_offset_rssi()
1689 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1693 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); in b43_nphy_scale_offset_rssi()
1699 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1703 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); in b43_nphy_scale_offset_rssi()
1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); in b43_nphy_scale_offset_rssi()
1709 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1713 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); in b43_nphy_scale_offset_rssi()
1719 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1721 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1725 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1727 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); in b43_nphy_scale_offset_rssi()
1732 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select_rev19() argument
1738 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev3_rssi_select() argument
1745 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); in b43_nphy_rev3_rssi_select()
1746 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); in b43_nphy_rev3_rssi_select()
1747 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); in b43_nphy_rev3_rssi_select()
1748 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); in b43_nphy_rev3_rssi_select()
1749 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); in b43_nphy_rev3_rssi_select()
1750 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); in b43_nphy_rev3_rssi_select()
1751 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); in b43_nphy_rev3_rssi_select()
1752 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); in b43_nphy_rev3_rssi_select()
1760 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); in b43_nphy_rev3_rssi_select()
1768 b43_phy_maskset(dev, reg, 0xFCFF, 0); in b43_nphy_rev3_rssi_select()
1773 b43_phy_maskset(dev, reg, 0xFFC3, 0); in b43_nphy_rev3_rssi_select()
1776 val = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 4 : 8; in b43_nphy_rev3_rssi_select()
1781 b43_phy_set(dev, reg, val); in b43_nphy_rev3_rssi_select()
1786 b43_phy_set(dev, reg, 0x0020); in b43_nphy_rev3_rssi_select()
1799 b43_phy_maskset(dev, reg, 0xFCFF, val); in b43_nphy_rev3_rssi_select()
1800 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); in b43_nphy_rev3_rssi_select()
1805 b43_current_band(dev->wl); in b43_nphy_rev3_rssi_select()
1807 if (dev->phy.rev < 7) { in b43_nphy_rev3_rssi_select()
1808 if (b43_nphy_ipa(dev)) in b43_nphy_rev3_rssi_select()
1814 b43_radio_write(dev, reg, val); in b43_nphy_rev3_rssi_select()
1820 b43_phy_set(dev, reg, 0x0200); in b43_nphy_rev3_rssi_select()
1827 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rev2_rssi_select() argument
1851 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1852 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1855 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, in b43_nphy_rev2_rssi_select()
1857 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, in b43_nphy_rev2_rssi_select()
1862 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); in b43_nphy_rev2_rssi_select()
1864 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1867 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1872 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1875 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1878 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); in b43_nphy_rev2_rssi_select()
1880 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1885 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, in b43_nphy_rev2_rssi_select()
1890 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_rev2_rssi_select()
1893 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1899 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, in b43_nphy_rssi_select() argument
1902 if (dev->phy.rev >= 19) in b43_nphy_rssi_select()
1903 b43_nphy_rssi_select_rev19(dev, code, type); in b43_nphy_rssi_select()
1904 else if (dev->phy.rev >= 3) in b43_nphy_rssi_select()
1905 b43_nphy_rev3_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1907 b43_nphy_rev2_rssi_select(dev, code, type); in b43_nphy_rssi_select()
1911 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, in b43_nphy_set_rssi_2055_vcm() argument
1918 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1920 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1923 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, in b43_nphy_set_rssi_2055_vcm()
1925 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1930 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1933 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, in b43_nphy_set_rssi_2055_vcm()
1940 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, in b43_nphy_poll_rssi() argument
1950 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
1951 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1952 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1953 save_regs_phy[2] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1955 save_regs_phy[3] = b43_phy_read(dev, in b43_nphy_poll_rssi()
1957 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_poll_rssi()
1958 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1959 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); in b43_nphy_poll_rssi()
1960 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); in b43_nphy_poll_rssi()
1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1964 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_poll_rssi()
1965 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_poll_rssi()
1966 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); in b43_nphy_poll_rssi()
1967 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); in b43_nphy_poll_rssi()
1968 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); in b43_nphy_poll_rssi()
1969 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); in b43_nphy_poll_rssi()
1974 b43_nphy_rssi_select(dev, 5, rssi_type); in b43_nphy_poll_rssi()
1976 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1977 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); in b43_nphy_poll_rssi()
1978 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); in b43_nphy_poll_rssi()
1985 if (dev->phy.rev < 2) { in b43_nphy_poll_rssi()
1986 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); in b43_nphy_poll_rssi()
1987 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); in b43_nphy_poll_rssi()
1989 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); in b43_nphy_poll_rssi()
1990 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); in b43_nphy_poll_rssi()
2001 if (dev->phy.rev < 2) in b43_nphy_poll_rssi()
2002 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); in b43_nphy_poll_rssi()
2004 if (dev->phy.rev >= 3) { in b43_nphy_poll_rssi()
2005 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2006 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2007 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, in b43_nphy_poll_rssi()
2009 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, in b43_nphy_poll_rssi()
2011 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); in b43_nphy_poll_rssi()
2012 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); in b43_nphy_poll_rssi()
2013 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); in b43_nphy_poll_rssi()
2014 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); in b43_nphy_poll_rssi()
2016 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2017 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); in b43_nphy_poll_rssi()
2018 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); in b43_nphy_poll_rssi()
2019 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); in b43_nphy_poll_rssi()
2020 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); in b43_nphy_poll_rssi()
2021 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); in b43_nphy_poll_rssi()
2022 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); in b43_nphy_poll_rssi()
2029 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) in b43_nphy_rev3_rssi_cal() argument
2031 struct b43_phy *phy = &dev->phy; in b43_nphy_rev3_rssi_cal()
2032 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev3_rssi_cal()
2080 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2089 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev3_rssi_cal()
2090 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev3_rssi_cal()
2091 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2092 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev3_rssi_cal()
2094 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev3_rssi_cal()
2095 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev3_rssi_cal()
2097 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); in b43_nphy_rev3_rssi_cal()
2099 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); in b43_nphy_rev3_rssi_cal()
2100 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); in b43_nphy_rev3_rssi_cal()
2102 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2103 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2106 b43_nphy_rf_ctl_override_one_to_many(dev, in b43_nphy_rev3_rssi_cal()
2109 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2110 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2111 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2112 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2114 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2117 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2119 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2123 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2124 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2125 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2126 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2127 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_rev3_rssi_cal()
2128 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2129 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2131 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2132 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2136 rx_core_state = b43_nphy_get_rx_core_state(dev); in b43_nphy_rev3_rssi_cal()
2141 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, in b43_nphy_rev3_rssi_cal()
2143 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, in b43_nphy_rev3_rssi_cal()
2148 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2149 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2154 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2156 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); in b43_nphy_rev3_rssi_cal()
2182 if (dev->phy.rev >= 7) in b43_nphy_rev3_rssi_cal()
2183 b43_radio_maskset(dev, in b43_nphy_rev3_rssi_cal()
2188 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, in b43_nphy_rev3_rssi_cal()
2201 b43_nphy_scale_offset_rssi(dev, 0, offset[i], in b43_nphy_rev3_rssi_cal()
2212 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2214 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2216 b43_nphy_poll_rssi(dev, i, poll_results, 8); in b43_nphy_rev3_rssi_cal()
2224 b43_nphy_scale_offset_rssi(dev, 0, in b43_nphy_rev3_rssi_cal()
2231 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); in b43_nphy_rev3_rssi_cal()
2232 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); in b43_nphy_rev3_rssi_cal()
2234 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev3_rssi_cal()
2236 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); in b43_nphy_rev3_rssi_cal()
2237 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); in b43_nphy_rev3_rssi_cal()
2238 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); in b43_nphy_rev3_rssi_cal()
2240 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rev3_rssi_cal()
2241 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); in b43_nphy_rev3_rssi_cal()
2242 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev3_rssi_cal()
2245 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); in b43_nphy_rev3_rssi_cal()
2248 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_rev3_rssi_cal()
2255 if (dev->phy.rev >= 7) { in b43_nphy_rev3_rssi_cal()
2256 rssical_radio_regs[0] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2258 rssical_radio_regs[1] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2261 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | in b43_nphy_rev3_rssi_cal()
2263 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | in b43_nphy_rev3_rssi_cal()
2266 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2267 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2268 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2269 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2270 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2271 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2272 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); in b43_nphy_rev3_rssi_cal()
2273 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); in b43_nphy_rev3_rssi_cal()
2274 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2275 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2276 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2277 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); in b43_nphy_rev3_rssi_cal()
2280 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_rev3_rssi_cal()
2286 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev3_rssi_cal()
2287 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev3_rssi_cal()
2291 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) in b43_nphy_rev2_rssi_cal() argument
2322 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev2_rssi_cal()
2323 b43_nphy_classifier(dev, 7, 4); in b43_nphy_rev2_rssi_cal()
2324 b43_nphy_read_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2325 b43_nphy_write_clip_detection(dev, clip_off); in b43_nphy_rev2_rssi_cal()
2327 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_rev2_rssi_cal()
2332 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev2_rssi_cal()
2333 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2334 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); in b43_nphy_rev2_rssi_cal()
2335 b43_radio_write(dev, B2055_C1_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2337 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_rev2_rssi_cal()
2338 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2339 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); in b43_nphy_rev2_rssi_cal()
2340 b43_radio_write(dev, B2055_C2_PD_RXTX, val); in b43_nphy_rev2_rssi_cal()
2342 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2343 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2344 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2345 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2346 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2347 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2349 b43_nphy_rssi_select(dev, 5, type); in b43_nphy_rev2_rssi_cal()
2350 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); in b43_nphy_rev2_rssi_cal()
2351 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); in b43_nphy_rev2_rssi_cal()
2358 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); in b43_nphy_rev2_rssi_cal()
2359 b43_nphy_poll_rssi(dev, type, results[vcm], 8); in b43_nphy_rev2_rssi_cal()
2390 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); in b43_nphy_rev2_rssi_cal()
2406 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, in b43_nphy_rev2_rssi_cal()
2410 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); in b43_nphy_rev2_rssi_cal()
2411 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); in b43_nphy_rev2_rssi_cal()
2415 b43_nphy_rssi_select(dev, 1, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2418 b43_nphy_rssi_select(dev, 1, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2421 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2424 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2430 b43_nphy_rssi_select(dev, 2, N_RSSI_NB); in b43_nphy_rev2_rssi_cal()
2433 b43_nphy_rssi_select(dev, 2, N_RSSI_W1); in b43_nphy_rev2_rssi_cal()
2436 b43_nphy_rssi_select(dev, 2, N_RSSI_W2); in b43_nphy_rev2_rssi_cal()
2440 b43_nphy_rssi_select(dev, 0, type); in b43_nphy_rev2_rssi_cal()
2442 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); in b43_nphy_rev2_rssi_cal()
2443 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); in b43_nphy_rev2_rssi_cal()
2444 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); in b43_nphy_rev2_rssi_cal()
2445 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); in b43_nphy_rev2_rssi_cal()
2447 b43_nphy_classifier(dev, 7, class); in b43_nphy_rev2_rssi_cal()
2448 b43_nphy_write_clip_detection(dev, clip_state); in b43_nphy_rev2_rssi_cal()
2451 b43_nphy_reset_cca(dev); in b43_nphy_rev2_rssi_cal()
2458 static void b43_nphy_rssi_cal(struct b43_wldev *dev) in b43_nphy_rssi_cal() argument
2460 if (dev->phy.rev >= 19) { in b43_nphy_rssi_cal()
2462 } else if (dev->phy.rev >= 3) { in b43_nphy_rssi_cal()
2463 b43_nphy_rev3_rssi_cal(dev); in b43_nphy_rssi_cal()
2465 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); in b43_nphy_rssi_cal()
2466 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); in b43_nphy_rssi_cal()
2467 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); in b43_nphy_rssi_cal()
2475 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev19() argument
2480 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev7() argument
2485 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev3() argument
2487 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_gain_ctl_workarounds_rev3()
2497 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) in b43_nphy_gain_ctl_workarounds_rev3()
2501 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); in b43_nphy_gain_ctl_workarounds_rev3()
2502 if (ghz5 && dev->phy.rev >= 5) in b43_nphy_gain_ctl_workarounds_rev3()
2507 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); in b43_nphy_gain_ctl_workarounds_rev3()
2510 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2511 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev3()
2513 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2515 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2517 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2518 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2519 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2520 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2521 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2523 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, in b43_nphy_gain_ctl_workarounds_rev3()
2525 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2527 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, in b43_nphy_gain_ctl_workarounds_rev3()
2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2530 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2532 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2533 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2534 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2535 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2536 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2537 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2538 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2539 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2540 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2541 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2542 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2543 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2545 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2546 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2548 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, in b43_nphy_gain_ctl_workarounds_rev3()
2551 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2552 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2553 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2554 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2555 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2556 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2558 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); in b43_nphy_gain_ctl_workarounds_rev3()
2559 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); in b43_nphy_gain_ctl_workarounds_rev3()
2560 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); in b43_nphy_gain_ctl_workarounds_rev3()
2561 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2562 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); in b43_nphy_gain_ctl_workarounds_rev3()
2563 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2565 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev3()
2567 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev3()
2570 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds_rev1_2() argument
2572 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_gain_ctl_workarounds_rev1_2()
2581 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2582 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2585 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2586 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2588 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2590 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2591 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2592 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2593 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2597 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2599 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, in b43_nphy_gain_ctl_workarounds_rev1_2()
2602 if (!b43_is_40mhz(dev)) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2603 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2605 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2607 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2609 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, in b43_nphy_gain_ctl_workarounds_rev1_2()
2613 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev1_2()
2616 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ && in b43_nphy_gain_ctl_workarounds_rev1_2()
2617 b43_is_40mhz(dev)) in b43_nphy_gain_ctl_workarounds_rev1_2()
2622 code = b43_is_40mhz(dev) ? 6 : 7; in b43_nphy_gain_ctl_workarounds_rev1_2()
2626 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2628 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, in b43_nphy_gain_ctl_workarounds_rev1_2()
2631 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2634 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); in b43_nphy_gain_ctl_workarounds_rev1_2()
2636 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_gain_ctl_workarounds_rev1_2()
2639 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); in b43_nphy_gain_ctl_workarounds_rev1_2()
2640 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2641 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2642 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2643 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2645 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); in b43_nphy_gain_ctl_workarounds_rev1_2()
2646 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2647 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2648 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2649 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2651 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2654 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_gain_ctl_workarounds_rev1_2()
2658 if (dev->phy.rev == 2) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2660 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_gain_ctl_workarounds_rev1_2()
2664 b43_phy_write(dev, in b43_nphy_gain_ctl_workarounds_rev1_2()
2670 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); in b43_nphy_gain_ctl_workarounds_rev1_2()
2671 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, in b43_nphy_gain_ctl_workarounds_rev1_2()
2675 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_gain_ctl_workarounds_rev1_2()
2676 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); in b43_nphy_gain_ctl_workarounds_rev1_2()
2680 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) in b43_nphy_gain_ctl_workarounds() argument
2682 if (dev->phy.rev >= 19) in b43_nphy_gain_ctl_workarounds()
2683 b43_nphy_gain_ctl_workarounds_rev19(dev); in b43_nphy_gain_ctl_workarounds()
2684 else if (dev->phy.rev >= 7) in b43_nphy_gain_ctl_workarounds()
2685 b43_nphy_gain_ctl_workarounds_rev7(dev); in b43_nphy_gain_ctl_workarounds()
2686 else if (dev->phy.rev >= 3) in b43_nphy_gain_ctl_workarounds()
2687 b43_nphy_gain_ctl_workarounds_rev3(dev); in b43_nphy_gain_ctl_workarounds()
2689 b43_nphy_gain_ctl_workarounds_rev1_2(dev); in b43_nphy_gain_ctl_workarounds()
2692 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev7plus() argument
2694 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev7plus()
2695 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev7plus()
2723 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev7plus()
2724 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); in b43_nphy_workarounds_rev7plus()
2725 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev7plus()
2726 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); in b43_nphy_workarounds_rev7plus()
2727 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); in b43_nphy_workarounds_rev7plus()
2728 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev7plus()
2731 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); in b43_nphy_workarounds_rev7plus()
2732 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); in b43_nphy_workarounds_rev7plus()
2733 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); in b43_nphy_workarounds_rev7plus()
2734 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); in b43_nphy_workarounds_rev7plus()
2735 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); in b43_nphy_workarounds_rev7plus()
2736 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); in b43_nphy_workarounds_rev7plus()
2737 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); in b43_nphy_workarounds_rev7plus()
2738 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); in b43_nphy_workarounds_rev7plus()
2739 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); in b43_nphy_workarounds_rev7plus()
2740 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); in b43_nphy_workarounds_rev7plus()
2741 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); in b43_nphy_workarounds_rev7plus()
2742 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2743 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2744 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2745 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2751 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); in b43_nphy_workarounds_rev7plus()
2752 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); in b43_nphy_workarounds_rev7plus()
2754 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); in b43_nphy_workarounds_rev7plus()
2755 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); in b43_nphy_workarounds_rev7plus()
2759 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); in b43_nphy_workarounds_rev7plus()
2761 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); in b43_nphy_workarounds_rev7plus()
2763 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); in b43_nphy_workarounds_rev7plus()
2764 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); in b43_nphy_workarounds_rev7plus()
2765 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev7plus()
2767 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev7plus()
2768 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2769 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2771 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev7plus()
2773 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev7plus()
2774 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev7plus()
2777 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2778 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2781 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2782 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2783 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2786 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); in b43_nphy_workarounds_rev7plus()
2787 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); in b43_nphy_workarounds_rev7plus()
2789 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
2790 bool ghz2 = b43_current_band(dev->wl) == NL80211_BAND_2GHZ; in b43_nphy_workarounds_rev7plus()
2795 if (phy->rev == 8 && b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
2818 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2929 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), in b43_nphy_workarounds_rev7plus()
2931 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), in b43_nphy_workarounds_rev7plus()
2933 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), in b43_nphy_workarounds_rev7plus()
2935 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), in b43_nphy_workarounds_rev7plus()
2937 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), in b43_nphy_workarounds_rev7plus()
2939 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), in b43_nphy_workarounds_rev7plus()
2941 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), in b43_nphy_workarounds_rev7plus()
2943 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), in b43_nphy_workarounds_rev7plus()
2948 b43_phy_write(dev, 0x32F, 0x3); in b43_nphy_workarounds_rev7plus()
2951 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); in b43_nphy_workarounds_rev7plus()
2956 b43_radio_write(dev, 0x5, 0x05); in b43_nphy_workarounds_rev7plus()
2957 b43_radio_write(dev, 0x6, 0x30); in b43_nphy_workarounds_rev7plus()
2958 b43_radio_write(dev, 0x7, 0x00); in b43_nphy_workarounds_rev7plus()
2959 b43_radio_set(dev, 0x4f, 0x1); in b43_nphy_workarounds_rev7plus()
2960 b43_radio_set(dev, 0xd4, 0x1); in b43_nphy_workarounds_rev7plus()
2969 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2972 b43_radio_write(dev, 0x5F, bias); in b43_nphy_workarounds_rev7plus()
2973 b43_radio_write(dev, 0x64, conv); in b43_nphy_workarounds_rev7plus()
2974 b43_radio_write(dev, 0x66, filt); in b43_nphy_workarounds_rev7plus()
2976 b43_radio_write(dev, 0xE8, bias); in b43_nphy_workarounds_rev7plus()
2977 b43_radio_write(dev, 0xE9, conv); in b43_nphy_workarounds_rev7plus()
2978 b43_radio_write(dev, 0xEB, filt); in b43_nphy_workarounds_rev7plus()
2984 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev7plus()
2985 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev7plus()
2990 b43_radio_write(dev, 0x51, in b43_nphy_workarounds_rev7plus()
2993 b43_radio_write(dev, 0xd6, in b43_nphy_workarounds_rev7plus()
3001 b43_radio_write(dev, 0x64, in b43_nphy_workarounds_rev7plus()
3003 b43_radio_write(dev, 0x5F, in b43_nphy_workarounds_rev7plus()
3005 b43_radio_write(dev, 0x66, in b43_nphy_workarounds_rev7plus()
3007 b43_radio_write(dev, 0x59, in b43_nphy_workarounds_rev7plus()
3009 b43_radio_write(dev, 0x80, in b43_nphy_workarounds_rev7plus()
3012 b43_radio_write(dev, 0x69, in b43_nphy_workarounds_rev7plus()
3014 b43_radio_write(dev, 0xE8, in b43_nphy_workarounds_rev7plus()
3016 b43_radio_write(dev, 0xEB, in b43_nphy_workarounds_rev7plus()
3018 b43_radio_write(dev, 0xDE, in b43_nphy_workarounds_rev7plus()
3020 b43_radio_write(dev, 0x105, in b43_nphy_workarounds_rev7plus()
3027 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev7plus()
3028 b43_radio_write(dev, 0x5F, 0x14); in b43_nphy_workarounds_rev7plus()
3029 b43_radio_write(dev, 0xE8, 0x12); in b43_nphy_workarounds_rev7plus()
3031 b43_radio_write(dev, 0x5F, 0x16); in b43_nphy_workarounds_rev7plus()
3032 b43_radio_write(dev, 0xE8, 0x16); in b43_nphy_workarounds_rev7plus()
3039 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); in b43_nphy_workarounds_rev7plus()
3040 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); in b43_nphy_workarounds_rev7plus()
3041 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); in b43_nphy_workarounds_rev7plus()
3042 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); in b43_nphy_workarounds_rev7plus()
3043 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); in b43_nphy_workarounds_rev7plus()
3044 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); in b43_nphy_workarounds_rev7plus()
3045 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); in b43_nphy_workarounds_rev7plus()
3046 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); in b43_nphy_workarounds_rev7plus()
3054 b43_radio_write(dev, 0x7D, 0xFF); in b43_nphy_workarounds_rev7plus()
3055 b43_radio_write(dev, 0xFE, 0xFF); in b43_nphy_workarounds_rev7plus()
3062 b43_radio_write(dev, 0x5c, 0x61); in b43_nphy_workarounds_rev7plus()
3063 b43_radio_write(dev, 0x51, 0x70); in b43_nphy_workarounds_rev7plus()
3065 b43_radio_write(dev, 0xe1, 0x61); in b43_nphy_workarounds_rev7plus()
3066 b43_radio_write(dev, 0xd6, 0x70); in b43_nphy_workarounds_rev7plus()
3073 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); in b43_nphy_workarounds_rev7plus()
3074 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); in b43_nphy_workarounds_rev7plus()
3077 b43_radio_write(dev, 0x1a1, 0x00); in b43_nphy_workarounds_rev7plus()
3078 b43_radio_write(dev, 0x1a2, 0x3f); in b43_nphy_workarounds_rev7plus()
3079 b43_radio_write(dev, 0x1a6, 0x3f); in b43_nphy_workarounds_rev7plus()
3081 b43_radio_write(dev, 0x1a7, 0x00); in b43_nphy_workarounds_rev7plus()
3082 b43_radio_write(dev, 0x1ab, 0x3f); in b43_nphy_workarounds_rev7plus()
3083 b43_radio_write(dev, 0x1ac, 0x3f); in b43_nphy_workarounds_rev7plus()
3087 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); in b43_nphy_workarounds_rev7plus()
3088 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); in b43_nphy_workarounds_rev7plus()
3089 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); in b43_nphy_workarounds_rev7plus()
3090 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); in b43_nphy_workarounds_rev7plus()
3092 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); in b43_nphy_workarounds_rev7plus()
3093 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); in b43_nphy_workarounds_rev7plus()
3094 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); in b43_nphy_workarounds_rev7plus()
3095 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); in b43_nphy_workarounds_rev7plus()
3096 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); in b43_nphy_workarounds_rev7plus()
3097 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); in b43_nphy_workarounds_rev7plus()
3099 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); in b43_nphy_workarounds_rev7plus()
3100 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); in b43_nphy_workarounds_rev7plus()
3101 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); in b43_nphy_workarounds_rev7plus()
3102 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); in b43_nphy_workarounds_rev7plus()
3105 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); in b43_nphy_workarounds_rev7plus()
3107 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); in b43_nphy_workarounds_rev7plus()
3108 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3109 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); in b43_nphy_workarounds_rev7plus()
3110 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); in b43_nphy_workarounds_rev7plus()
3111 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3112 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); in b43_nphy_workarounds_rev7plus()
3113 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); in b43_nphy_workarounds_rev7plus()
3115 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3116 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3117 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3119 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3120 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3121 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3123 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev7plus()
3137 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) in b43_nphy_workarounds_rev3plus() argument
3139 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_workarounds_rev3plus()
3140 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev3plus()
3172 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); in b43_nphy_workarounds_rev3plus()
3173 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); in b43_nphy_workarounds_rev3plus()
3175 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev3plus()
3177 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev3plus()
3179 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev3plus()
3180 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); in b43_nphy_workarounds_rev3plus()
3181 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev3plus()
3182 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); in b43_nphy_workarounds_rev3plus()
3183 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); in b43_nphy_workarounds_rev3plus()
3184 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev3plus()
3186 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3187 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3190 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, in b43_nphy_workarounds_rev3plus()
3194 if (b43_nphy_ipa(dev)) in b43_nphy_workarounds_rev3plus()
3195 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev3plus()
3199 if (b43_nphy_ipa(dev)) { in b43_nphy_workarounds_rev3plus()
3204 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, in b43_nphy_workarounds_rev3plus()
3208 tmp16 = (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? in b43_nphy_workarounds_rev3plus()
3210 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); in b43_nphy_workarounds_rev3plus()
3212 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); in b43_nphy_workarounds_rev3plus()
3214 if (!b43_is_40mhz(dev)) { in b43_nphy_workarounds_rev3plus()
3215 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); in b43_nphy_workarounds_rev3plus()
3216 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); in b43_nphy_workarounds_rev3plus()
3218 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); in b43_nphy_workarounds_rev3plus()
3219 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); in b43_nphy_workarounds_rev3plus()
3222 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev3plus()
3224 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); in b43_nphy_workarounds_rev3plus()
3225 b43_ntab_write(dev, B43_NTAB16(8, 16), 2); in b43_nphy_workarounds_rev3plus()
3227 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3235 if (!(dev->phy.rev >= 4 && in b43_nphy_workarounds_rev3plus()
3236 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3241 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3242 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3243 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3244 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3247 if (dev->phy.rev >= 6) { in b43_nphy_workarounds_rev3plus()
3248 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_workarounds_rev3plus()
3253 } else if (dev->phy.rev == 5) { in b43_nphy_workarounds_rev3plus()
3257 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3258 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3259 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3260 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3264 if (b43_current_band(dev->wl) != NL80211_BAND_2GHZ) { in b43_nphy_workarounds_rev3plus()
3285 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3286 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3288 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3289 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3293 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3294 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3295 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3296 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3297 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3298 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3299 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3300 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3301 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3302 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3303 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3304 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3309 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) || in b43_nphy_workarounds_rev3plus()
3311 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) in b43_nphy_workarounds_rev3plus()
3315 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); in b43_nphy_workarounds_rev3plus()
3316 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); in b43_nphy_workarounds_rev3plus()
3317 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); in b43_nphy_workarounds_rev3plus()
3319 if (dev->phy.rev == 4 && in b43_nphy_workarounds_rev3plus()
3320 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_workarounds_rev3plus()
3321 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3323 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, in b43_nphy_workarounds_rev3plus()
3328 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); in b43_nphy_workarounds_rev3plus()
3329 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); in b43_nphy_workarounds_rev3plus()
3330 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); in b43_nphy_workarounds_rev3plus()
3331 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); in b43_nphy_workarounds_rev3plus()
3332 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3333 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3334 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3335 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3336 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3337 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3338 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3339 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3341 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) { in b43_nphy_workarounds_rev3plus()
3346 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) in b43_nphy_workarounds_rev1_2() argument
3348 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_workarounds_rev1_2()
3349 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds_rev1_2()
3359 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { in b43_nphy_workarounds_rev1_2()
3364 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ && in b43_nphy_workarounds_rev1_2()
3366 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3367 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3369 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3370 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3373 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); in b43_nphy_workarounds_rev1_2()
3374 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); in b43_nphy_workarounds_rev1_2()
3375 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3376 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3377 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3380 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3381 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); in b43_nphy_workarounds_rev1_2()
3382 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); in b43_nphy_workarounds_rev1_2()
3383 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3384 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3385 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); in b43_nphy_workarounds_rev1_2()
3386 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); in b43_nphy_workarounds_rev1_2()
3389 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_workarounds_rev1_2()
3390 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_workarounds_rev1_2()
3391 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_workarounds_rev1_2()
3392 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_workarounds_rev1_2()
3394 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); in b43_nphy_workarounds_rev1_2()
3395 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); in b43_nphy_workarounds_rev1_2()
3397 b43_nphy_gain_ctl_workarounds(dev); in b43_nphy_workarounds_rev1_2()
3399 if (dev->phy.rev < 2) { in b43_nphy_workarounds_rev1_2()
3400 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) in b43_nphy_workarounds_rev1_2()
3401 b43_hf_write(dev, b43_hf_read(dev) | in b43_nphy_workarounds_rev1_2()
3403 } else if (dev->phy.rev == 2) { in b43_nphy_workarounds_rev1_2()
3404 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); in b43_nphy_workarounds_rev1_2()
3405 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); in b43_nphy_workarounds_rev1_2()
3408 if (dev->phy.rev < 2) in b43_nphy_workarounds_rev1_2()
3409 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, in b43_nphy_workarounds_rev1_2()
3413 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); in b43_nphy_workarounds_rev1_2()
3414 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); in b43_nphy_workarounds_rev1_2()
3415 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); in b43_nphy_workarounds_rev1_2()
3416 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); in b43_nphy_workarounds_rev1_2()
3417 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); in b43_nphy_workarounds_rev1_2()
3418 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); in b43_nphy_workarounds_rev1_2()
3420 if (dev->phy.rev < 3) { in b43_nphy_workarounds_rev1_2()
3421 b43_phy_mask(dev, B43_NPHY_PIL_DW1, in b43_nphy_workarounds_rev1_2()
3423 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); in b43_nphy_workarounds_rev1_2()
3424 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); in b43_nphy_workarounds_rev1_2()
3425 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); in b43_nphy_workarounds_rev1_2()
3428 if (dev->phy.rev == 2) in b43_nphy_workarounds_rev1_2()
3429 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, in b43_nphy_workarounds_rev1_2()
3434 static void b43_nphy_workarounds(struct b43_wldev *dev) in b43_nphy_workarounds() argument
3436 struct b43_phy *phy = &dev->phy; in b43_nphy_workarounds()
3439 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_workarounds()
3440 b43_nphy_classifier(dev, 1, 0); in b43_nphy_workarounds()
3442 b43_nphy_classifier(dev, 1, 1); in b43_nphy_workarounds()
3445 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_workarounds()
3447 b43_phy_set(dev, B43_NPHY_IQFLIP, in b43_nphy_workarounds()
3451 if (dev->phy.rev >= 7) in b43_nphy_workarounds()
3452 b43_nphy_workarounds_rev7plus(dev); in b43_nphy_workarounds()
3453 else if (dev->phy.rev >= 3) in b43_nphy_workarounds()
3454 b43_nphy_workarounds_rev3plus(dev); in b43_nphy_workarounds()
3456 b43_nphy_workarounds_rev1_2(dev); in b43_nphy_workarounds()
3459 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_workarounds()
3470 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, in b43_nphy_tx_tone() argument
3473 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); in b43_nphy_tx_tone()
3476 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, in b43_nphy_tx_tone()
3482 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) in b43_nphy_update_txrx_chain() argument
3484 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_txrx_chain()
3497 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_update_txrx_chain()
3502 b43_phy_set(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3505 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_nphy_update_txrx_chain()
3510 static void b43_nphy_stop_playback(struct b43_wldev *dev) in b43_nphy_stop_playback() argument
3512 struct b43_phy *phy = &dev->phy; in b43_nphy_stop_playback()
3513 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_stop_playback()
3517 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_stop_playback()
3519 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); in b43_nphy_stop_playback()
3521 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); in b43_nphy_stop_playback()
3523 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_stop_playback()
3525 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); in b43_nphy_stop_playback()
3529 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); in b43_nphy_stop_playback()
3535 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, in b43_nphy_stop_playback()
3538 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); in b43_nphy_stop_playback()
3543 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_stop_playback()
3547 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, in b43_nphy_iq_cal_gain_params() argument
3551 struct b43_phy *phy = &dev->phy; in b43_nphy_iq_cal_gain_params()
3555 if (dev->phy.rev >= 3) { in b43_nphy_iq_cal_gain_params()
3574 indx = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? in b43_nphy_iq_cal_gain_params()
3596 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) in b43_nphy_tx_power_ctrl() argument
3598 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctrl()
3599 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctrl()
3602 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_tx_power_ctrl()
3605 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_ctrl()
3609 if (dev->phy.rev >= 3 && in b43_nphy_tx_power_ctrl()
3610 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & in b43_nphy_tx_power_ctrl()
3615 nphy->tx_pwr_idx[0] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3617 nphy->tx_pwr_idx[1] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3621 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); in b43_nphy_tx_power_ctrl()
3623 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3625 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); in b43_nphy_tx_power_ctrl()
3627 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3630 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctrl()
3632 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); in b43_nphy_tx_power_ctrl()
3634 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3635 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_ctrl()
3636 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_ctrl()
3638 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_ctrl()
3641 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3642 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3644 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3645 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_nphy_tx_power_ctrl()
3648 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3649 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3651 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, in b43_nphy_tx_power_ctrl()
3653 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, in b43_nphy_tx_power_ctrl()
3660 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3665 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); in b43_nphy_tx_power_ctrl()
3671 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3674 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctrl()
3678 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3682 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3689 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3693 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctrl()
3696 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctrl()
3697 b43_phy_maskset(dev, in b43_nphy_tx_power_ctrl()
3707 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctrl()
3708 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); in b43_nphy_tx_power_ctrl()
3709 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); in b43_nphy_tx_power_ctrl()
3711 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); in b43_nphy_tx_power_ctrl()
3714 if (dev->phy.rev == 2) in b43_nphy_tx_power_ctrl()
3715 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); in b43_nphy_tx_power_ctrl()
3716 else if (dev->phy.rev < 2) in b43_nphy_tx_power_ctrl()
3717 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); in b43_nphy_tx_power_ctrl()
3719 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) in b43_nphy_tx_power_ctrl()
3720 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); in b43_nphy_tx_power_ctrl()
3722 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctrl()
3723 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); in b43_nphy_tx_power_ctrl()
3724 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); in b43_nphy_tx_power_ctrl()
3729 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_ctrl()
3733 static void b43_nphy_tx_power_fix(struct b43_wldev *dev) in b43_nphy_tx_power_fix() argument
3735 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_fix()
3736 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_fix()
3737 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_fix()
3746 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_tx_power_fix()
3749 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_fix()
3751 } else if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3758 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_power_fix()
3775 if (dev->phy.rev < 7 && in b43_nphy_tx_power_fix()
3787 const u32 *table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_power_fix()
3793 if (dev->phy.rev >= 3) in b43_nphy_tx_power_fix()
3798 if (dev->phy.rev >= 7) in b43_nphy_tx_power_fix()
3804 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_fix()
3806 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_fix()
3808 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_fix()
3810 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_fix()
3814 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); in b43_nphy_tx_power_fix()
3816 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); in b43_nphy_tx_power_fix()
3818 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); in b43_nphy_tx_power_fix()
3820 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); in b43_nphy_tx_power_fix()
3825 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); in b43_nphy_tx_power_fix()
3827 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_fix()
3831 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, in b43_nphy_tx_power_fix()
3833 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); in b43_nphy_tx_power_fix()
3834 b43_phy_set(dev, reg, 0x4); in b43_nphy_tx_power_fix()
3838 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); in b43_nphy_tx_power_fix()
3841 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_fix()
3844 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) in b43_nphy_ipa_internal_tssi_setup() argument
3846 struct b43_phy *phy = &dev->phy; in b43_nphy_ipa_internal_tssi_setup()
3856 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3857 b43_radio_write(dev, r + 0x5, 0x5); in b43_nphy_ipa_internal_tssi_setup()
3858 b43_radio_write(dev, r + 0x9, 0xE); in b43_nphy_ipa_internal_tssi_setup()
3860 b43_radio_write(dev, r + 0xA, 0); in b43_nphy_ipa_internal_tssi_setup()
3862 b43_radio_write(dev, r + 0xB, 1); in b43_nphy_ipa_internal_tssi_setup()
3864 b43_radio_write(dev, r + 0xB, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3866 b43_radio_write(dev, r + 0x5, 0x9); in b43_nphy_ipa_internal_tssi_setup()
3867 b43_radio_write(dev, r + 0x9, 0xC); in b43_nphy_ipa_internal_tssi_setup()
3868 b43_radio_write(dev, r + 0xB, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3870 b43_radio_write(dev, r + 0xA, 1); in b43_nphy_ipa_internal_tssi_setup()
3872 b43_radio_write(dev, r + 0xA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3874 b43_radio_write(dev, r + 0x6, 0); in b43_nphy_ipa_internal_tssi_setup()
3875 b43_radio_write(dev, r + 0x7, 0); in b43_nphy_ipa_internal_tssi_setup()
3876 b43_radio_write(dev, r + 0x8, 3); in b43_nphy_ipa_internal_tssi_setup()
3877 b43_radio_write(dev, r + 0xC, 0); in b43_nphy_ipa_internal_tssi_setup()
3880 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_ipa_internal_tssi_setup()
3881 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); in b43_nphy_ipa_internal_tssi_setup()
3883 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); in b43_nphy_ipa_internal_tssi_setup()
3884 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); in b43_nphy_ipa_internal_tssi_setup()
3885 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); in b43_nphy_ipa_internal_tssi_setup()
3890 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); in b43_nphy_ipa_internal_tssi_setup()
3891 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); in b43_nphy_ipa_internal_tssi_setup()
3892 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); in b43_nphy_ipa_internal_tssi_setup()
3893 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); in b43_nphy_ipa_internal_tssi_setup()
3894 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); in b43_nphy_ipa_internal_tssi_setup()
3895 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); in b43_nphy_ipa_internal_tssi_setup()
3896 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); in b43_nphy_ipa_internal_tssi_setup()
3897 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_ipa_internal_tssi_setup()
3898 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3901 b43_radio_write(dev, r | B2056_TX_TSSIA, in b43_nphy_ipa_internal_tssi_setup()
3904 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3907 b43_radio_write(dev, r | B2056_TX_TSSIG, in b43_nphy_ipa_internal_tssi_setup()
3909 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3912 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, in b43_nphy_ipa_internal_tssi_setup()
3914 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3915 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3916 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, in b43_nphy_ipa_internal_tssi_setup()
3928 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_idle_tssi() argument
3930 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_idle_tssi()
3931 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_idle_tssi()
3939 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_idle_tssi()
3940 b43_nphy_ipa_internal_tssi_setup(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3943 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3945 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3947 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); in b43_nphy_tx_power_ctl_idle_tssi()
3949 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3950 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); in b43_nphy_tx_power_ctl_idle_tssi()
3952 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); in b43_nphy_tx_power_ctl_idle_tssi()
3953 b43_nphy_stop_playback(dev); in b43_nphy_tx_power_ctl_idle_tssi()
3955 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); in b43_nphy_tx_power_ctl_idle_tssi()
3958 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3960 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3962 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); in b43_nphy_tx_power_ctl_idle_tssi()
3979 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) in b43_nphy_tx_prepare_adjusted_power_table() argument
3981 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_prepare_adjusted_power_table()
4007 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { in b43_nphy_tx_prepare_adjusted_power_table()
4011 idx = b43_is_40mhz(dev) ? 52 : 4; in b43_nphy_tx_prepare_adjusted_power_table()
4015 idx = b43_is_40mhz(dev) ? 76 : 28; in b43_nphy_tx_prepare_adjusted_power_table()
4018 idx = b43_is_40mhz(dev) ? 84 : 36; in b43_nphy_tx_prepare_adjusted_power_table()
4021 idx = b43_is_40mhz(dev) ? 92 : 44; in b43_nphy_tx_prepare_adjusted_power_table()
4040 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) in b43_nphy_tx_power_ctl_setup() argument
4042 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_power_ctl_setup()
4043 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_power_ctl_setup()
4044 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_tx_power_ctl_setup()
4058 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4059 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4060 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4065 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_power_ctl_setup()
4067 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); in b43_nphy_tx_power_ctl_setup()
4068 if (dev->phy.rev >= 3) in b43_nphy_tx_power_ctl_setup()
4069 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4072 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4075 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4076 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4086 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_power_ctl_setup()
4128 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); in b43_nphy_tx_power_ctl_setup()
4134 if (dev->phy.rev >= 3) { in b43_nphy_tx_power_ctl_setup()
4136 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); in b43_nphy_tx_power_ctl_setup()
4137 if (dev->phy.rev >= 7) { in b43_nphy_tx_power_ctl_setup()
4140 if (b43_nphy_ipa(dev)) in b43_nphy_tx_power_ctl_setup()
4141 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 0xE : 0xC); in b43_nphy_tx_power_ctl_setup()
4144 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_power_ctl_setup()
4145 tmp = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 0xC : 0xE; in b43_nphy_tx_power_ctl_setup()
4146 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4148 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4151 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4153 b43_radio_write(dev, in b43_nphy_tx_power_ctl_setup()
4159 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_tx_power_ctl_setup()
4160 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4161 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_tx_power_ctl_setup()
4168 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4170 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4173 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, in b43_nphy_tx_power_ctl_setup()
4175 if (dev->phy.rev > 1) in b43_nphy_tx_power_ctl_setup()
4176 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, in b43_nphy_tx_power_ctl_setup()
4180 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_tx_power_ctl_setup()
4181 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4183 b43_phy_write(dev, B43_NPHY_TXPCTL_N, in b43_nphy_tx_power_ctl_setup()
4186 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, in b43_nphy_tx_power_ctl_setup()
4190 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, in b43_nphy_tx_power_ctl_setup()
4199 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) in b43_nphy_tx_power_ctl_setup()
4203 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); in b43_nphy_tx_power_ctl_setup()
4206 b43_nphy_tx_prepare_adjusted_power_table(dev); in b43_nphy_tx_power_ctl_setup()
4207 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4208 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); in b43_nphy_tx_power_ctl_setup()
4211 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_power_ctl_setup()
4214 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) in b43_nphy_tx_gain_table_upload() argument
4216 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_gain_table_upload()
4224 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_tx_gain_table_upload()
4228 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4229 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); in b43_nphy_tx_gain_table_upload()
4241 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); in b43_nphy_tx_gain_table_upload()
4255 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4261 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_tx_gain_table_upload()
4267 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4268 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); in b43_nphy_tx_gain_table_upload()
4273 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) in b43_nphy_pa_override() argument
4275 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_pa_override()
4280 nphy->rfctrl_intc1_save = b43_phy_read(dev, in b43_nphy_pa_override()
4282 nphy->rfctrl_intc2_save = b43_phy_read(dev, in b43_nphy_pa_override()
4284 band = b43_current_band(dev->wl); in b43_nphy_pa_override()
4285 if (dev->phy.rev >= 7) { in b43_nphy_pa_override()
4287 } else if (dev->phy.rev >= 3) { in b43_nphy_pa_override()
4298 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_pa_override()
4299 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_pa_override()
4301 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, in b43_nphy_pa_override()
4303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, in b43_nphy_pa_override()
4312 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) in b43_nphy_tx_lpf_bw() argument
4316 if (dev->phy.rev < 3 || dev->phy.rev >= 7) in b43_nphy_tx_lpf_bw()
4319 if (b43_nphy_ipa(dev)) in b43_nphy_tx_lpf_bw()
4320 tmp = b43_is_40mhz(dev) ? 5 : 4; in b43_nphy_tx_lpf_bw()
4322 tmp = b43_is_40mhz(dev) ? 3 : 1; in b43_nphy_tx_lpf_bw()
4323 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, in b43_nphy_tx_lpf_bw()
4326 if (b43_nphy_ipa(dev)) { in b43_nphy_tx_lpf_bw()
4327 tmp = b43_is_40mhz(dev) ? 4 : 1; in b43_nphy_tx_lpf_bw()
4328 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, in b43_nphy_tx_lpf_bw()
4334 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, in b43_nphy_rx_iq_est() argument
4340 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); in b43_nphy_rx_iq_est()
4341 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); in b43_nphy_rx_iq_est()
4343 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4345 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); in b43_nphy_rx_iq_est()
4347 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); in b43_nphy_rx_iq_est()
4350 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); in b43_nphy_rx_iq_est()
4352 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4353 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); in b43_nphy_rx_iq_est()
4354 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4355 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); in b43_nphy_rx_iq_est()
4356 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | in b43_nphy_rx_iq_est()
4357 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); in b43_nphy_rx_iq_est()
4359 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4360 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); in b43_nphy_rx_iq_est()
4361 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4362 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); in b43_nphy_rx_iq_est()
4363 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | in b43_nphy_rx_iq_est()
4364 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); in b43_nphy_rx_iq_est()
4373 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, in b43_nphy_rx_iq_coeffs() argument
4377 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); in b43_nphy_rx_iq_coeffs()
4378 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); in b43_nphy_rx_iq_coeffs()
4379 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); in b43_nphy_rx_iq_coeffs()
4380 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); in b43_nphy_rx_iq_coeffs()
4382 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); in b43_nphy_rx_iq_coeffs()
4383 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); in b43_nphy_rx_iq_coeffs()
4384 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); in b43_nphy_rx_iq_coeffs()
4385 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); in b43_nphy_rx_iq_coeffs()
4392 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
4394 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4396 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4398 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
4399 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4401 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4402 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4404 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
4405 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
4406 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
4407 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
4408 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
4409 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
4410 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4411 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4415 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
4418 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4420 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4422 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4423 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4425 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4426 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4428 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4429 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4430 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
4431 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
4432 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
4433 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
4434 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4435 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4437 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4438 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4440 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4443 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4445 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4447 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
4451 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4452 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4454 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4455 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4458 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4459 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4460 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4469 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
4471 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
4477 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) in b43_nphy_calc_rx_iq_comp() argument
4495 b43_nphy_rx_iq_coeffs(dev, false, &old); in b43_nphy_calc_rx_iq_comp()
4496 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4497 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); in b43_nphy_calc_rx_iq_comp()
4550 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4558 if (dev->phy.rev >= 3) { in b43_nphy_calc_rx_iq_comp()
4571 b43_nphy_rx_iq_coeffs(dev, true, &new); in b43_nphy_calc_rx_iq_comp()
4575 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) in b43_nphy_tx_iq_workaround() argument
4578 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); in b43_nphy_tx_iq_workaround()
4580 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); in b43_nphy_tx_iq_workaround()
4581 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); in b43_nphy_tx_iq_workaround()
4582 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); in b43_nphy_tx_iq_workaround()
4583 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); in b43_nphy_tx_iq_workaround()
4587 static void b43_nphy_spur_workaround(struct b43_wldev *dev) in b43_nphy_spur_workaround() argument
4589 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_spur_workaround()
4591 B43_WARN_ON(dev->phy.rev < 3); in b43_nphy_spur_workaround()
4594 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_spur_workaround()
4597 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_spur_workaround()
4601 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) in b43_nphy_tx_pwr_ctrl_coef_setup() argument
4603 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_pwr_ctrl_coef_setup()
4611 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_tx_pwr_ctrl_coef_setup()
4613 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_tx_pwr_ctrl_coef_setup()
4618 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4621 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4623 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4632 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, in b43_nphy_tx_pwr_ctrl_coef_setup()
4635 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4642 if (dev->phy.rev < 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4648 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, in b43_nphy_tx_pwr_ctrl_coef_setup()
4650 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, in b43_nphy_tx_pwr_ctrl_coef_setup()
4655 if (dev->phy.rev >= 3) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4656 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4658 b43_shm_write16(dev, B43_SHM_SHARED, in b43_nphy_tx_pwr_ctrl_coef_setup()
4663 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_tx_pwr_ctrl_coef_setup()
4670 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) in b43_nphy_restore_rssi_cal() argument
4672 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_rssi_cal()
4677 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_rssi_cal()
4689 if (dev->phy.rev >= 19) { in b43_nphy_restore_rssi_cal()
4691 } else if (dev->phy.rev >= 7) { in b43_nphy_restore_rssi_cal()
4692 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4694 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, in b43_nphy_restore_rssi_cal()
4697 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4699 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4703 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); in b43_nphy_restore_rssi_cal()
4704 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); in b43_nphy_restore_rssi_cal()
4705 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); in b43_nphy_restore_rssi_cal()
4706 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); in b43_nphy_restore_rssi_cal()
4708 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); in b43_nphy_restore_rssi_cal()
4709 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); in b43_nphy_restore_rssi_cal()
4710 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); in b43_nphy_restore_rssi_cal()
4711 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); in b43_nphy_restore_rssi_cal()
4713 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); in b43_nphy_restore_rssi_cal()
4714 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); in b43_nphy_restore_rssi_cal()
4715 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); in b43_nphy_restore_rssi_cal()
4716 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); in b43_nphy_restore_rssi_cal()
4719 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev19() argument
4724 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup_rev7() argument
4726 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup_rev7()
4727 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup_rev7()
4736 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); in b43_nphy_tx_cal_radio_setup_rev7()
4737 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); in b43_nphy_tx_cal_radio_setup_rev7()
4738 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); in b43_nphy_tx_cal_radio_setup_rev7()
4739 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); in b43_nphy_tx_cal_radio_setup_rev7()
4741 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); in b43_nphy_tx_cal_radio_setup_rev7()
4743 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); in b43_nphy_tx_cal_radio_setup_rev7()
4744 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); in b43_nphy_tx_cal_radio_setup_rev7()
4745 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); in b43_nphy_tx_cal_radio_setup_rev7()
4747 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup_rev7()
4748 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); in b43_nphy_tx_cal_radio_setup_rev7()
4749 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4750 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4751 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4752 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4754 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); in b43_nphy_tx_cal_radio_setup_rev7()
4756 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4758 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); in b43_nphy_tx_cal_radio_setup_rev7()
4760 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4761 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4762 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4763 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4766 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4768 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4770 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); in b43_nphy_tx_cal_radio_setup_rev7()
4772 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4778 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_radio_setup() argument
4780 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_radio_setup()
4781 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_radio_setup()
4787 b43_nphy_tx_cal_radio_setup_rev19(dev); in b43_nphy_tx_cal_radio_setup()
4789 b43_nphy_tx_cal_radio_setup_rev7(dev); in b43_nphy_tx_cal_radio_setup()
4795 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); in b43_nphy_tx_cal_radio_setup()
4796 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); in b43_nphy_tx_cal_radio_setup()
4797 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); in b43_nphy_tx_cal_radio_setup()
4798 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); in b43_nphy_tx_cal_radio_setup()
4799 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); in b43_nphy_tx_cal_radio_setup()
4800 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); in b43_nphy_tx_cal_radio_setup()
4801 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); in b43_nphy_tx_cal_radio_setup()
4802 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); in b43_nphy_tx_cal_radio_setup()
4803 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); in b43_nphy_tx_cal_radio_setup()
4804 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); in b43_nphy_tx_cal_radio_setup()
4805 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); in b43_nphy_tx_cal_radio_setup()
4807 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { in b43_nphy_tx_cal_radio_setup()
4808 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); in b43_nphy_tx_cal_radio_setup()
4809 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4810 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4811 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4812 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4814 b43_radio_write(dev, tmp | B2055_PADDRV, 4); in b43_nphy_tx_cal_radio_setup()
4815 b43_radio_write(dev, tmp | B2055_XOCTL1, 1); in b43_nphy_tx_cal_radio_setup()
4817 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4818 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); in b43_nphy_tx_cal_radio_setup()
4820 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4822 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); in b43_nphy_tx_cal_radio_setup()
4823 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4824 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4825 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4826 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4827 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); in b43_nphy_tx_cal_radio_setup()
4829 b43_radio_write(dev, tmp | B2055_PADDRV, 6); in b43_nphy_tx_cal_radio_setup()
4830 b43_radio_write(dev, tmp | B2055_XOCTL2, in b43_nphy_tx_cal_radio_setup()
4831 (dev->phy.rev < 5) ? 0x11 : 0x01); in b43_nphy_tx_cal_radio_setup()
4833 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4834 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4837 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); in b43_nphy_tx_cal_radio_setup()
4838 b43_radio_write(dev, tmp | B2055_XOMISC, 0); in b43_nphy_tx_cal_radio_setup()
4839 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); in b43_nphy_tx_cal_radio_setup()
4842 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4843 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4845 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4846 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4848 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4849 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4851 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); in b43_nphy_tx_cal_radio_setup()
4852 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4854 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4855 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); in b43_nphy_tx_cal_radio_setup()
4857 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & in b43_nphy_tx_cal_radio_setup()
4859 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4860 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4862 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4863 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4866 if (dev->phy.rev < 2) { in b43_nphy_tx_cal_radio_setup()
4867 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4868 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4870 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4871 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4877 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) in b43_nphy_update_tx_cal_ladder() argument
4879 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_update_tx_cal_ladder()
4891 b43_ntab_write(dev, B43_NTAB16(15, i), entry); in b43_nphy_update_tx_cal_ladder()
4895 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); in b43_nphy_update_tx_cal_ladder()
4899 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, in b43_nphy_pa_set_tx_dig_filter() argument
4907 b43_phy_write(dev, offset, filter[i]); in b43_nphy_pa_set_tx_dig_filter()
4911 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_ext_pa_set_tx_dig_filters() argument
4913 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, in b43_nphy_ext_pa_set_tx_dig_filters()
4918 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) in b43_nphy_int_pa_set_tx_dig_filters() argument
4930 b43_nphy_pa_set_tx_dig_filter(dev, offset[i], in b43_nphy_int_pa_set_tx_dig_filters()
4934 if (dev->phy.rev == 16) in b43_nphy_int_pa_set_tx_dig_filters()
4935 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4938 if (dev->phy.rev == 17) { in b43_nphy_int_pa_set_tx_dig_filters()
4939 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4940 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, in b43_nphy_int_pa_set_tx_dig_filters()
4944 if (b43_is_40mhz(dev)) { in b43_nphy_int_pa_set_tx_dig_filters()
4945 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4948 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_int_pa_set_tx_dig_filters()
4949 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4951 if (dev->phy.channel == 14) in b43_nphy_int_pa_set_tx_dig_filters()
4952 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4958 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) in b43_nphy_get_tx_gains() argument
4960 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_get_tx_gains()
4970 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_get_tx_gains()
4971 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); in b43_nphy_get_tx_gains()
4973 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_get_tx_gains()
4976 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
4982 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
4997 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5000 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5005 table = b43_nphy_get_tx_gain_table(dev); in b43_nphy_get_tx_gains()
5009 if (dev->phy.rev >= 7) { in b43_nphy_get_tx_gains()
5015 } else if (dev->phy.rev >= 3) { in b43_nphy_get_tx_gains()
5033 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_cleanup() argument
5035 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_cleanup()
5037 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_cleanup()
5038 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5039 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5041 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5042 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5043 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5044 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); in b43_nphy_tx_cal_phy_cleanup()
5046 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); in b43_nphy_tx_cal_phy_cleanup()
5047 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); in b43_nphy_tx_cal_phy_cleanup()
5048 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); in b43_nphy_tx_cal_phy_cleanup()
5049 b43_nphy_reset_cca(dev); in b43_nphy_tx_cal_phy_cleanup()
5051 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5052 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5053 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); in b43_nphy_tx_cal_phy_cleanup()
5054 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); in b43_nphy_tx_cal_phy_cleanup()
5055 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); in b43_nphy_tx_cal_phy_cleanup()
5056 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); in b43_nphy_tx_cal_phy_cleanup()
5057 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); in b43_nphy_tx_cal_phy_cleanup()
5062 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) in b43_nphy_tx_cal_phy_setup() argument
5064 struct b43_phy *phy = &dev->phy; in b43_nphy_tx_cal_phy_setup()
5065 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_tx_cal_phy_setup()
5066 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; in b43_nphy_tx_cal_phy_setup()
5069 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_tx_cal_phy_setup()
5070 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); in b43_nphy_tx_cal_phy_setup()
5071 if (dev->phy.rev >= 3) { in b43_nphy_tx_cal_phy_setup()
5072 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5073 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5075 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); in b43_nphy_tx_cal_phy_setup()
5077 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5079 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5081 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5083 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_nphy_tx_cal_phy_setup()
5084 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_tx_cal_phy_setup()
5087 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); in b43_nphy_tx_cal_phy_setup()
5089 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); in b43_nphy_tx_cal_phy_setup()
5091 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); in b43_nphy_tx_cal_phy_setup()
5093 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); in b43_nphy_tx_cal_phy_setup()
5094 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5095 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5098 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5101 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, in b43_nphy_tx_cal_phy_setup()
5103 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); in b43_nphy_tx_cal_phy_setup()
5104 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); in b43_nphy_tx_cal_phy_setup()
5106 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); in b43_nphy_tx_cal_phy_setup()
5107 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); in b43_nphy_tx_cal_phy_setup()
5108 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5109 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5111 tmp = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_tx_cal_phy_setup()
5113 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5116 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5121 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5124 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5127 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); in b43_nphy_tx_cal_phy_setup()
5128 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_tx_cal_phy_setup()
5129 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5130 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5132 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5133 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5138 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5139 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5140 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_tx_cal_phy_setup()
5142 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); in b43_nphy_tx_cal_phy_setup()
5143 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); in b43_nphy_tx_cal_phy_setup()
5146 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); in b43_nphy_tx_cal_phy_setup()
5147 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); in b43_nphy_tx_cal_phy_setup()
5150 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); in b43_nphy_tx_cal_phy_setup()
5151 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_tx_cal_phy_setup()
5152 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); in b43_nphy_tx_cal_phy_setup()
5153 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) in b43_nphy_tx_cal_phy_setup()
5157 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); in b43_nphy_tx_cal_phy_setup()
5158 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); in b43_nphy_tx_cal_phy_setup()
5163 static void b43_nphy_save_cal(struct b43_wldev *dev) in b43_nphy_save_cal() argument
5165 struct b43_phy *phy = &dev->phy; in b43_nphy_save_cal()
5166 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_save_cal()
5174 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_save_cal()
5176 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_save_cal()
5188 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); in b43_nphy_save_cal()
5193 txcal_radio_regs[0] = b43_radio_read(dev, in b43_nphy_save_cal()
5195 txcal_radio_regs[1] = b43_radio_read(dev, in b43_nphy_save_cal()
5197 txcal_radio_regs[4] = b43_radio_read(dev, in b43_nphy_save_cal()
5199 txcal_radio_regs[5] = b43_radio_read(dev, in b43_nphy_save_cal()
5201 txcal_radio_regs[2] = b43_radio_read(dev, in b43_nphy_save_cal()
5203 txcal_radio_regs[3] = b43_radio_read(dev, in b43_nphy_save_cal()
5205 txcal_radio_regs[6] = b43_radio_read(dev, in b43_nphy_save_cal()
5207 txcal_radio_regs[7] = b43_radio_read(dev, in b43_nphy_save_cal()
5210 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); in b43_nphy_save_cal()
5211 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); in b43_nphy_save_cal()
5212 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); in b43_nphy_save_cal()
5213 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); in b43_nphy_save_cal()
5214 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); in b43_nphy_save_cal()
5215 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); in b43_nphy_save_cal()
5216 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); in b43_nphy_save_cal()
5217 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); in b43_nphy_save_cal()
5219 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); in b43_nphy_save_cal()
5220 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); in b43_nphy_save_cal()
5221 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); in b43_nphy_save_cal()
5222 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); in b43_nphy_save_cal()
5224 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; in b43_nphy_save_cal()
5226 cfg80211_get_chandef_type(dev->phy.chandef); in b43_nphy_save_cal()
5227 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); in b43_nphy_save_cal()
5230 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_save_cal()
5234 static void b43_nphy_restore_cal(struct b43_wldev *dev) in b43_nphy_restore_cal() argument
5236 struct b43_phy *phy = &dev->phy; in b43_nphy_restore_cal()
5237 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_restore_cal()
5247 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5259 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); in b43_nphy_restore_cal()
5262 if (dev->phy.rev >= 3) in b43_nphy_restore_cal()
5268 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); in b43_nphy_restore_cal()
5269 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); in b43_nphy_restore_cal()
5270 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); in b43_nphy_restore_cal()
5272 if (dev->phy.rev < 2) in b43_nphy_restore_cal()
5273 b43_nphy_tx_iq_workaround(dev); in b43_nphy_restore_cal()
5275 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_restore_cal()
5287 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, in b43_nphy_restore_cal()
5289 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, in b43_nphy_restore_cal()
5291 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, in b43_nphy_restore_cal()
5293 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5295 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, in b43_nphy_restore_cal()
5297 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, in b43_nphy_restore_cal()
5299 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, in b43_nphy_restore_cal()
5301 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, in b43_nphy_restore_cal()
5304 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5305 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5306 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5307 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5308 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); in b43_nphy_restore_cal()
5309 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); in b43_nphy_restore_cal()
5310 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); in b43_nphy_restore_cal()
5311 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); in b43_nphy_restore_cal()
5313 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5314 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5315 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5316 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5318 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); in b43_nphy_restore_cal()
5322 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, in b43_nphy_cal_tx_iq_lo() argument
5326 struct b43_phy *phy = &dev->phy; in b43_nphy_cal_tx_iq_lo()
5327 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_cal_tx_iq_lo()
5344 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_cal_tx_iq_lo()
5346 if (dev->phy.rev >= 4) { in b43_nphy_cal_tx_iq_lo()
5351 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5354 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); in b43_nphy_cal_tx_iq_lo()
5358 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); in b43_nphy_cal_tx_iq_lo()
5360 b43_nphy_tx_cal_radio_setup(dev); in b43_nphy_cal_tx_iq_lo()
5361 b43_nphy_tx_cal_phy_setup(dev); in b43_nphy_cal_tx_iq_lo()
5363 phy6or5x = dev->phy.rev >= 6 || in b43_nphy_cal_tx_iq_lo()
5364 (dev->phy.rev == 5 && nphy->ipa2g_on && in b43_nphy_cal_tx_iq_lo()
5365 b43_current_band(dev->wl) == NL80211_BAND_2GHZ); in b43_nphy_cal_tx_iq_lo()
5367 if (b43_is_40mhz(dev)) { in b43_nphy_cal_tx_iq_lo()
5368 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5370 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5373 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5375 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, in b43_nphy_cal_tx_iq_lo()
5383 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); in b43_nphy_cal_tx_iq_lo()
5385 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); in b43_nphy_cal_tx_iq_lo()
5388 if (!b43_is_40mhz(dev)) in b43_nphy_cal_tx_iq_lo()
5394 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, in b43_nphy_cal_tx_iq_lo()
5397 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); in b43_nphy_cal_tx_iq_lo()
5403 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5409 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5413 if (dev->phy.rev >= 3) { in b43_nphy_cal_tx_iq_lo()
5423 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); in b43_nphy_cal_tx_iq_lo()
5426 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5431 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5448 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5453 if (dev->phy.rev >= 3) in b43_nphy_cal_tx_iq_lo()
5463 b43_nphy_update_tx_cal_ladder(dev, core); in b43_nphy_cal_tx_iq_lo()
5468 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); in b43_nphy_cal_tx_iq_lo()
5471 buffer[0] = b43_ntab_read(dev, in b43_nphy_cal_tx_iq_lo()
5475 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), in b43_nphy_cal_tx_iq_lo()
5479 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); in b43_nphy_cal_tx_iq_lo()
5481 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); in b43_nphy_cal_tx_iq_lo()
5487 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5489 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, in b43_nphy_cal_tx_iq_lo()
5499 last = (dev->phy.rev < 3) ? 6 : 7; in b43_nphy_cal_tx_iq_lo()
5502 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5503 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); in b43_nphy_cal_tx_iq_lo()
5504 if (dev->phy.rev < 3) { in b43_nphy_cal_tx_iq_lo()
5510 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_cal_tx_iq_lo()
5512 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, in b43_nphy_cal_tx_iq_lo()
5514 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_cal_tx_iq_lo()
5516 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_cal_tx_iq_lo()
5519 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5521 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5530 if (dev->phy.rev < 3) in b43_nphy_cal_tx_iq_lo()
5532 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, in b43_nphy_cal_tx_iq_lo()
5536 b43_nphy_stop_playback(dev); in b43_nphy_cal_tx_iq_lo()
5537 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); in b43_nphy_cal_tx_iq_lo()
5540 b43_nphy_tx_cal_phy_cleanup(dev); in b43_nphy_cal_tx_iq_lo()
5541 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5543 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) in b43_nphy_cal_tx_iq_lo()
5544 b43_nphy_tx_iq_workaround(dev); in b43_nphy_cal_tx_iq_lo()
5546 if (dev->phy.rev >= 4) in b43_nphy_cal_tx_iq_lo()
5549 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_cal_tx_iq_lo()
5555 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) in b43_nphy_reapply_tx_cal_coeffs() argument
5557 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_reapply_tx_cal_coeffs()
5563 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || in b43_nphy_reapply_tx_cal_coeffs()
5564 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) in b43_nphy_reapply_tx_cal_coeffs()
5567 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); in b43_nphy_reapply_tx_cal_coeffs()
5576 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, in b43_nphy_reapply_tx_cal_coeffs()
5580 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, in b43_nphy_reapply_tx_cal_coeffs()
5582 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, in b43_nphy_reapply_tx_cal_coeffs()
5584 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, in b43_nphy_reapply_tx_cal_coeffs()
5590 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev2_cal_rx_iq() argument
5593 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_rev2_cal_rx_iq()
5616 b43_nphy_stay_in_carrier_search(dev, 1); in b43_nphy_rev2_cal_rx_iq()
5618 if (dev->phy.rev < 2) in b43_nphy_rev2_cal_rx_iq()
5619 b43_nphy_reapply_tx_cal_coeffs(dev); in b43_nphy_rev2_cal_rx_iq()
5620 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5622 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); in b43_nphy_rev2_cal_rx_iq()
5625 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); in b43_nphy_rev2_cal_rx_iq()
5638 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); in b43_nphy_rev2_cal_rx_iq()
5639 tmp[2] = b43_phy_read(dev, afectl_core); in b43_nphy_rev2_cal_rx_iq()
5640 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); in b43_nphy_rev2_cal_rx_iq()
5641 tmp[4] = b43_phy_read(dev, rfctl[0]); in b43_nphy_rev2_cal_rx_iq()
5642 tmp[5] = b43_phy_read(dev, rfctl[1]); in b43_nphy_rev2_cal_rx_iq()
5644 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, in b43_nphy_rev2_cal_rx_iq()
5647 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, in b43_nphy_rev2_cal_rx_iq()
5649 b43_phy_set(dev, afectl_core, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5650 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5652 band = b43_current_band(dev->wl); in b43_nphy_rev2_cal_rx_iq()
5656 b43_phy_write(dev, rfctl[0], 0x140); in b43_nphy_rev2_cal_rx_iq()
5658 b43_phy_write(dev, rfctl[0], 0x110); in b43_nphy_rev2_cal_rx_iq()
5661 b43_phy_write(dev, rfctl[0], 0x180); in b43_nphy_rev2_cal_rx_iq()
5663 b43_phy_write(dev, rfctl[0], 0x120); in b43_nphy_rev2_cal_rx_iq()
5667 b43_phy_write(dev, rfctl[1], 0x148); in b43_nphy_rev2_cal_rx_iq()
5669 b43_phy_write(dev, rfctl[1], 0x114); in b43_nphy_rev2_cal_rx_iq()
5672 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5674 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5712 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, in b43_nphy_rev2_cal_rx_iq()
5714 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5715 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5718 ret = b43_nphy_tx_tone(dev, 4000, in b43_nphy_rev2_cal_rx_iq()
5723 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, in b43_nphy_rev2_cal_rx_iq()
5729 b43_nphy_rx_iq_est(dev, &est, 1024, 32, in b43_nphy_rev2_cal_rx_iq()
5740 b43_nphy_calc_rx_iq_comp(dev, 1 << i); in b43_nphy_rev2_cal_rx_iq()
5742 b43_nphy_stop_playback(dev); in b43_nphy_rev2_cal_rx_iq()
5749 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5750 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5751 b43_phy_write(dev, rfctl[1], tmp[5]); in b43_nphy_rev2_cal_rx_iq()
5752 b43_phy_write(dev, rfctl[0], tmp[4]); in b43_nphy_rev2_cal_rx_iq()
5753 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); in b43_nphy_rev2_cal_rx_iq()
5754 b43_phy_write(dev, afectl_core, tmp[2]); in b43_nphy_rev2_cal_rx_iq()
5755 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); in b43_nphy_rev2_cal_rx_iq()
5761 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); in b43_nphy_rev2_cal_rx_iq()
5762 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_rev2_cal_rx_iq()
5763 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5765 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_rev2_cal_rx_iq()
5770 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_rev3_cal_rx_iq() argument
5777 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, in b43_nphy_cal_rx_iq() argument
5780 if (dev->phy.rev >= 7) in b43_nphy_cal_rx_iq()
5783 if (dev->phy.rev >= 3) in b43_nphy_cal_rx_iq()
5784 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5786 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); in b43_nphy_cal_rx_iq()
5790 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) in b43_nphy_set_rx_core_state() argument
5792 struct b43_phy *phy = &dev->phy; in b43_nphy_set_rx_core_state()
5801 b43_mac_suspend(dev); in b43_nphy_set_rx_core_state()
5804 b43_nphy_stay_in_carrier_search(dev, true); in b43_nphy_set_rx_core_state()
5806 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, in b43_nphy_set_rx_core_state()
5810 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); in b43_nphy_set_rx_core_state()
5811 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5815 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); in b43_nphy_set_rx_core_state()
5816 if (dev->phy.rev >= 3) { in b43_nphy_set_rx_core_state()
5821 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_nphy_set_rx_core_state()
5824 b43_nphy_stay_in_carrier_search(dev, false); in b43_nphy_set_rx_core_state()
5826 b43_mac_enable(dev); in b43_nphy_set_rx_core_state()
5829 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, in b43_nphy_op_recalc_txpower() argument
5832 struct b43_phy *phy = &dev->phy; in b43_nphy_op_recalc_txpower()
5833 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_op_recalc_txpower()
5834 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_recalc_txpower()
5843 b43_ppr_clear(dev, ppr); in b43_nphy_op_recalc_txpower()
5846 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); in b43_nphy_op_recalc_txpower()
5852 b43_ppr_apply_max(dev, ppr, max); in b43_nphy_op_recalc_txpower()
5853 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_nphy_op_recalc_txpower()
5854 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", in b43_nphy_op_recalc_txpower()
5855 Q52_ARG(b43_ppr_get_max(dev, ppr))); in b43_nphy_op_recalc_txpower()
5861 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_op_recalc_txpower()
5865 b43_ppr_add(dev, ppr, -hw_gain); in b43_nphy_op_recalc_txpower()
5869 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); in b43_nphy_op_recalc_txpower()
5872 b43_mac_suspend(dev); in b43_nphy_op_recalc_txpower()
5873 b43_nphy_tx_power_ctl_setup(dev); in b43_nphy_op_recalc_txpower()
5874 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { in b43_nphy_op_recalc_txpower()
5875 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); in b43_nphy_op_recalc_txpower()
5876 b43_read32(dev, B43_MMIO_MACCTL); in b43_nphy_op_recalc_txpower()
5879 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); in b43_nphy_op_recalc_txpower()
5880 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) in b43_nphy_op_recalc_txpower()
5881 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); in b43_nphy_op_recalc_txpower()
5882 b43_mac_enable(dev); in b43_nphy_op_recalc_txpower()
5895 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) in b43_nphy_update_mimo_config() argument
5897 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); in b43_nphy_update_mimo_config()
5905 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); in b43_nphy_update_mimo_config()
5909 static void b43_nphy_bphy_init(struct b43_wldev *dev) in b43_nphy_bphy_init() argument
5916 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); in b43_nphy_bphy_init()
5921 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); in b43_nphy_bphy_init()
5924 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); in b43_nphy_bphy_init()
5928 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) in b43_nphy_superswitch_init() argument
5930 if (dev->phy.rev >= 7) in b43_nphy_superswitch_init()
5933 if (dev->phy.rev >= 3) { in b43_nphy_superswitch_init()
5937 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); in b43_nphy_superswitch_init()
5938 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); in b43_nphy_superswitch_init()
5939 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); in b43_nphy_superswitch_init()
5940 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); in b43_nphy_superswitch_init()
5943 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); in b43_nphy_superswitch_init()
5944 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); in b43_nphy_superswitch_init()
5946 switch (dev->dev->bus_type) { in b43_nphy_superswitch_init()
5949 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, in b43_nphy_superswitch_init()
5955 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, in b43_nphy_superswitch_init()
5961 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); in b43_nphy_superswitch_init()
5962 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); in b43_nphy_superswitch_init()
5963 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), in b43_nphy_superswitch_init()
5967 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_superswitch_init()
5968 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_superswitch_init()
5969 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_superswitch_init()
5970 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_superswitch_init()
5976 static int b43_phy_initn(struct b43_wldev *dev) in b43_phy_initn() argument
5978 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_phy_initn()
5979 struct b43_phy *phy = &dev->phy; in b43_phy_initn()
5989 if ((dev->phy.rev >= 3) && in b43_phy_initn()
5991 (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) { in b43_phy_initn()
5992 switch (dev->dev->bus_type) { in b43_phy_initn()
5995 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, in b43_phy_initn()
6001 chipco_set32(&dev->dev->sdev->bus->chipco, in b43_phy_initn()
6007 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || in b43_phy_initn()
6012 b43_nphy_tables_init(dev); in b43_phy_initn()
6017 if (dev->phy.rev >= 3) { in b43_phy_initn()
6018 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); in b43_phy_initn()
6019 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6021 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); in b43_phy_initn()
6022 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); in b43_phy_initn()
6023 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); in b43_phy_initn()
6024 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); in b43_phy_initn()
6030 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); in b43_phy_initn()
6031 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); in b43_phy_initn()
6033 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6035 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); in b43_phy_initn()
6036 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); in b43_phy_initn()
6037 if (dev->phy.rev < 6) { in b43_phy_initn()
6038 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); in b43_phy_initn()
6039 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); in b43_phy_initn()
6041 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, in b43_phy_initn()
6044 if (dev->phy.rev >= 3) in b43_phy_initn()
6045 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); in b43_phy_initn()
6046 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); in b43_phy_initn()
6048 if (dev->phy.rev <= 2) { in b43_phy_initn()
6049 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; in b43_phy_initn()
6050 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, in b43_phy_initn()
6054 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); in b43_phy_initn()
6055 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); in b43_phy_initn()
6058 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_phy_initn()
6059 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) in b43_phy_initn()
6060 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); in b43_phy_initn()
6062 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); in b43_phy_initn()
6063 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); in b43_phy_initn()
6064 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); in b43_phy_initn()
6065 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); in b43_phy_initn()
6068 b43_nphy_update_mimo_config(dev, nphy->preamble_override); in b43_phy_initn()
6070 b43_nphy_update_txrx_chain(dev); in b43_phy_initn()
6073 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); in b43_phy_initn()
6074 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); in b43_phy_initn()
6077 if (b43_nphy_ipa(dev)) { in b43_phy_initn()
6078 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); in b43_phy_initn()
6079 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, in b43_phy_initn()
6081 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); in b43_phy_initn()
6082 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, in b43_phy_initn()
6084 b43_nphy_int_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6086 b43_nphy_ext_pa_set_tx_dig_filters(dev); in b43_phy_initn()
6089 b43_nphy_workarounds(dev); in b43_phy_initn()
6092 b43_phy_force_clock(dev, 1); in b43_phy_initn()
6093 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); in b43_phy_initn()
6094 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6095 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); in b43_phy_initn()
6096 b43_phy_force_clock(dev, 0); in b43_phy_initn()
6098 b43_mac_phy_clock_set(dev, true); in b43_phy_initn()
6101 b43_nphy_pa_override(dev, false); in b43_phy_initn()
6102 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); in b43_phy_initn()
6103 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); in b43_phy_initn()
6104 b43_nphy_pa_override(dev, true); in b43_phy_initn()
6107 b43_nphy_classifier(dev, 0, 0); in b43_phy_initn()
6108 b43_nphy_read_clip_detection(dev, clip); in b43_phy_initn()
6109 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6110 b43_nphy_bphy_init(dev); in b43_phy_initn()
6113 b43_nphy_tx_power_ctrl(dev, false); in b43_phy_initn()
6114 b43_nphy_tx_power_fix(dev); in b43_phy_initn()
6115 b43_nphy_tx_power_ctl_idle_tssi(dev); in b43_phy_initn()
6116 b43_nphy_tx_power_ctl_setup(dev); in b43_phy_initn()
6117 b43_nphy_tx_gain_table_upload(dev); in b43_phy_initn()
6120 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); in b43_phy_initn()
6127 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6133 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6135 b43_nphy_restore_rssi_cal(dev); in b43_phy_initn()
6137 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6141 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_phy_initn()
6150 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6153 b43_nphy_superswitch_init(dev, true); in b43_phy_initn()
6155 b43_nphy_rssi_cal(dev); in b43_phy_initn()
6162 target = b43_nphy_get_tx_gains(dev); in b43_phy_initn()
6164 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) in b43_phy_initn()
6165 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) in b43_phy_initn()
6166 b43_nphy_save_cal(dev); in b43_phy_initn()
6171 b43_nphy_restore_cal(dev); in b43_phy_initn()
6175 b43_nphy_tx_pwr_ctrl_coef_setup(dev); in b43_phy_initn()
6176 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); in b43_phy_initn()
6177 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); in b43_phy_initn()
6178 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); in b43_phy_initn()
6180 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); in b43_phy_initn()
6181 b43_nphy_tx_lpf_bw(dev); in b43_phy_initn()
6183 b43_nphy_spur_workaround(dev); in b43_phy_initn()
6192 static void b43_chantab_phy_upload(struct b43_wldev *dev, in b43_chantab_phy_upload() argument
6195 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); in b43_chantab_phy_upload()
6196 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); in b43_chantab_phy_upload()
6197 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); in b43_chantab_phy_upload()
6198 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); in b43_chantab_phy_upload()
6199 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); in b43_chantab_phy_upload()
6200 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); in b43_chantab_phy_upload()
6204 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) in b43_nphy_pmu_spur_avoid() argument
6206 switch (dev->dev->bus_type) { in b43_nphy_pmu_spur_avoid()
6209 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, in b43_nphy_pmu_spur_avoid()
6215 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, in b43_nphy_pmu_spur_avoid()
6223 static void b43_nphy_channel_setup(struct b43_wldev *dev, in b43_nphy_channel_setup() argument
6227 struct b43_phy *phy = &dev->phy; in b43_nphy_channel_setup()
6228 struct b43_phy_n *nphy = dev->phy.n; in b43_nphy_channel_setup()
6234 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6236 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6237 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6239 b43_phy_set(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6241 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6242 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6244 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); in b43_nphy_channel_setup()
6245 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); in b43_nphy_channel_setup()
6246 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); in b43_nphy_channel_setup()
6248 b43_phy_mask(dev, B43_PHY_B_BBCFG, in b43_nphy_channel_setup()
6250 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); in b43_nphy_channel_setup()
6253 b43_chantab_phy_upload(dev, e); in b43_nphy_channel_setup()
6256 b43_nphy_classifier(dev, 2, 0); in b43_nphy_channel_setup()
6257 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); in b43_nphy_channel_setup()
6259 b43_nphy_classifier(dev, 2, 2); in b43_nphy_channel_setup()
6261 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); in b43_nphy_channel_setup()
6265 b43_nphy_tx_power_fix(dev); in b43_nphy_channel_setup()
6267 if (dev->phy.rev < 3) in b43_nphy_channel_setup()
6268 b43_nphy_adjust_lna_gain_table(dev); in b43_nphy_channel_setup()
6270 b43_nphy_tx_lpf_bw(dev); in b43_nphy_channel_setup()
6272 if (dev->phy.rev >= 3 && in b43_nphy_channel_setup()
6273 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { in b43_nphy_channel_setup()
6276 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { in b43_nphy_channel_setup()
6287 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6295 if (!b43_is_40mhz(dev)) { /* 20MHz */ in b43_nphy_channel_setup()
6301 spuravoid = dev->dev->chip_id == 0x4716; in b43_nphy_channel_setup()
6305 b43_nphy_pmu_spur_avoid(dev, spuravoid); in b43_nphy_channel_setup()
6307 b43_mac_switch_freq(dev, spuravoid); in b43_nphy_channel_setup()
6309 if (dev->phy.rev == 3 || dev->phy.rev == 4) in b43_nphy_channel_setup()
6310 b43_wireless_core_phy_pll_reset(dev); in b43_nphy_channel_setup()
6313 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); in b43_nphy_channel_setup()
6315 b43_phy_mask(dev, B43_NPHY_BBCFG, in b43_nphy_channel_setup()
6318 b43_nphy_reset_cca(dev); in b43_nphy_channel_setup()
6323 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); in b43_nphy_channel_setup()
6326 b43_nphy_spur_workaround(dev); in b43_nphy_channel_setup()
6330 static int b43_nphy_set_channel(struct b43_wldev *dev, in b43_nphy_set_channel() argument
6334 struct b43_phy *phy = &dev->phy; in b43_nphy_set_channel()
6347 r2057_get_chantabent_rev7(dev, channel->center_freq, in b43_nphy_set_channel()
6352 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, in b43_nphy_set_channel()
6357 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, in b43_nphy_set_channel()
6374 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6376 b43_phy_set(dev, 0x310, 0x8000); in b43_nphy_set_channel()
6378 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); in b43_nphy_set_channel()
6380 b43_phy_mask(dev, 0x310, (u16)~0x8000); in b43_nphy_set_channel()
6391 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); in b43_nphy_set_channel()
6392 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); in b43_nphy_set_channel()
6395 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); in b43_nphy_set_channel()
6396 b43_nphy_channel_setup(dev, phy_regs, channel); in b43_nphy_set_channel()
6399 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); in b43_nphy_set_channel()
6400 b43_radio_2056_setup(dev, tabent_r3); in b43_nphy_set_channel()
6401 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); in b43_nphy_set_channel()
6404 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); in b43_nphy_set_channel()
6405 b43_radio_2055_setup(dev, tabent_r2); in b43_nphy_set_channel()
6406 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); in b43_nphy_set_channel()
6416 static int b43_nphy_op_allocate(struct b43_wldev *dev) in b43_nphy_op_allocate() argument
6424 dev->phy.n = nphy; in b43_nphy_op_allocate()
6429 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) in b43_nphy_op_prepare_structs() argument
6431 struct b43_phy *phy = &dev->phy; in b43_nphy_op_prepare_structs()
6433 struct ssb_sprom *sprom = dev->dev->bus_sprom; in b43_nphy_op_prepare_structs()
6452 if (dev->phy.rev >= 3 || in b43_nphy_op_prepare_structs()
6453 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && in b43_nphy_op_prepare_structs()
6454 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { in b43_nphy_op_prepare_structs()
6458 if (dev->phy.rev >= 2 && in b43_nphy_op_prepare_structs()
6462 if (dev->dev->bus_type == B43_BUS_SSB && in b43_nphy_op_prepare_structs()
6463 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { in b43_nphy_op_prepare_structs()
6465 dev->dev->sdev->bus->host_pci; in b43_nphy_op_prepare_structs()
6476 if (dev->phy.rev >= 3) { in b43_nphy_op_prepare_structs()
6482 static void b43_nphy_op_free(struct b43_wldev *dev) in b43_nphy_op_free() argument
6484 struct b43_phy *phy = &dev->phy; in b43_nphy_op_free()
6491 static int b43_nphy_op_init(struct b43_wldev *dev) in b43_nphy_op_init() argument
6493 return b43_phy_initn(dev); in b43_nphy_op_init()
6496 static inline void check_phyreg(struct b43_wldev *dev, u16 offset) in check_phyreg() argument
6501 b43err(dev->wl, "Invalid OFDM PHY access at " in check_phyreg()
6507 b43err(dev->wl, "Invalid EXT-G PHY access at " in check_phyreg()
6514 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, in b43_nphy_op_maskset() argument
6517 check_phyreg(dev, reg); in b43_nphy_op_maskset()
6518 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_nphy_op_maskset()
6519 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); in b43_nphy_op_maskset()
6520 dev->phy.writes_counter = 1; in b43_nphy_op_maskset()
6523 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_nphy_op_radio_read() argument
6526 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_read()
6528 if (dev->phy.rev >= 7) in b43_nphy_op_radio_read()
6533 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_read()
6534 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_nphy_op_radio_read()
6537 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_nphy_op_radio_write() argument
6540 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); in b43_nphy_op_radio_write()
6542 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_nphy_op_radio_write()
6543 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_nphy_op_radio_write()
6547 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, in b43_nphy_op_software_rfkill() argument
6550 struct b43_phy *phy = &dev->phy; in b43_nphy_op_software_rfkill()
6552 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) in b43_nphy_op_software_rfkill()
6553 b43err(dev->wl, "MAC not suspended\n"); in b43_nphy_op_software_rfkill()
6559 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6564 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, in b43_nphy_op_software_rfkill()
6567 b43_radio_mask(dev, 0x09, ~0x2); in b43_nphy_op_software_rfkill()
6569 b43_radio_write(dev, 0x204D, 0); in b43_nphy_op_software_rfkill()
6570 b43_radio_write(dev, 0x2053, 0); in b43_nphy_op_software_rfkill()
6571 b43_radio_write(dev, 0x2058, 0); in b43_nphy_op_software_rfkill()
6572 b43_radio_write(dev, 0x205E, 0); in b43_nphy_op_software_rfkill()
6573 b43_radio_mask(dev, 0x2062, ~0xF0); in b43_nphy_op_software_rfkill()
6574 b43_radio_write(dev, 0x2064, 0); in b43_nphy_op_software_rfkill()
6576 b43_radio_write(dev, 0x304D, 0); in b43_nphy_op_software_rfkill()
6577 b43_radio_write(dev, 0x3053, 0); in b43_nphy_op_software_rfkill()
6578 b43_radio_write(dev, 0x3058, 0); in b43_nphy_op_software_rfkill()
6579 b43_radio_write(dev, 0x305E, 0); in b43_nphy_op_software_rfkill()
6580 b43_radio_mask(dev, 0x3062, ~0xF0); in b43_nphy_op_software_rfkill()
6581 b43_radio_write(dev, 0x3064, 0); in b43_nphy_op_software_rfkill()
6587 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6588 b43_radio_2057_init(dev); in b43_nphy_op_software_rfkill()
6589 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6591 if (!dev->phy.radio_on) in b43_nphy_op_software_rfkill()
6592 b43_radio_init2056(dev); in b43_nphy_op_software_rfkill()
6593 b43_switch_channel(dev, dev->phy.channel); in b43_nphy_op_software_rfkill()
6595 b43_radio_init2055(dev); in b43_nphy_op_software_rfkill()
6601 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) in b43_nphy_op_switch_analog() argument
6603 struct b43_phy *phy = &dev->phy; in b43_nphy_op_switch_analog()
6611 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6612 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6613 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6614 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6616 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); in b43_nphy_op_switch_analog()
6617 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); in b43_nphy_op_switch_analog()
6618 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6619 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); in b43_nphy_op_switch_analog()
6622 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); in b43_nphy_op_switch_analog()
6626 static int b43_nphy_op_switch_channel(struct b43_wldev *dev, in b43_nphy_op_switch_channel() argument
6629 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; in b43_nphy_op_switch_channel()
6631 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); in b43_nphy_op_switch_channel()
6633 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { in b43_nphy_op_switch_channel()
6641 return b43_nphy_set_channel(dev, channel, channel_type); in b43_nphy_op_switch_channel()
6644 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) in b43_nphy_op_get_default_chan() argument
6646 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) in b43_nphy_op_get_default_chan()