62 static void b43_radio_2064_channel_setup(struct b43_wldev *dev)  in b43_radio_2064_channel_setup()  argument
66 	b43_radio_set(dev, 0x09d, 0x4);  in b43_radio_2064_channel_setup()
67 	b43_radio_write(dev, 0x09e, 0xf);  in b43_radio_2064_channel_setup()
70 	b43_radio_write(dev, 0x02a, 0xb);  in b43_radio_2064_channel_setup()
71 	b43_radio_maskset(dev, 0x030, ~0x3, 0xa);  in b43_radio_2064_channel_setup()
72 	b43_radio_maskset(dev, 0x091, ~0x3, 0);  in b43_radio_2064_channel_setup()
73 	b43_radio_maskset(dev, 0x038, ~0xf, 0x7);  in b43_radio_2064_channel_setup()
74 	b43_radio_maskset(dev, 0x030, ~0xc, 0x8);  in b43_radio_2064_channel_setup()
75 	b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);  in b43_radio_2064_channel_setup()
76 	b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);  in b43_radio_2064_channel_setup()
77 	b43_radio_write(dev, 0x06c, 0x80);  in b43_radio_2064_channel_setup()
79 	save[0] = b43_radio_read(dev, 0x044);  in b43_radio_2064_channel_setup()
80 	save[1] = b43_radio_read(dev, 0x12b);  in b43_radio_2064_channel_setup()
82 	b43_radio_set(dev, 0x044, 0x7);  in b43_radio_2064_channel_setup()
83 	b43_radio_set(dev, 0x12b, 0xe);  in b43_radio_2064_channel_setup()
87 	b43_radio_write(dev, 0x040, 0xfb);  in b43_radio_2064_channel_setup()
89 	b43_radio_write(dev, 0x041, 0x9a);  in b43_radio_2064_channel_setup()
90 	b43_radio_write(dev, 0x042, 0xa3);  in b43_radio_2064_channel_setup()
91 	b43_radio_write(dev, 0x043, 0x0c);  in b43_radio_2064_channel_setup()
95 	b43_radio_set(dev, 0x044, 0x0c);  in b43_radio_2064_channel_setup()
98 	b43_radio_write(dev, 0x044, save[0]);  in b43_radio_2064_channel_setup()
99 	b43_radio_write(dev, 0x12b, save[1]);  in b43_radio_2064_channel_setup()
101 	if (dev->phy.rev == 1) {  in b43_radio_2064_channel_setup()
103 		b43_radio_write(dev, 0x038, 0x0);  in b43_radio_2064_channel_setup()
104 		b43_radio_write(dev, 0x091, 0x7);  in b43_radio_2064_channel_setup()
109 static void b43_radio_2064_init(struct b43_wldev *dev)  in b43_radio_2064_init()  argument
111 	if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {  in b43_radio_2064_init()
112 		b43_radio_write(dev, 0x09c, 0x0020);  in b43_radio_2064_init()
113 		b43_radio_write(dev, 0x105, 0x0008);  in b43_radio_2064_init()
117 	b43_radio_write(dev, 0x032, 0x0062);  in b43_radio_2064_init()
118 	b43_radio_write(dev, 0x033, 0x0019);  in b43_radio_2064_init()
119 	b43_radio_write(dev, 0x090, 0x0010);  in b43_radio_2064_init()
120 	b43_radio_write(dev, 0x010, 0x0000);  in b43_radio_2064_init()
121 	if (dev->phy.rev == 1) {  in b43_radio_2064_init()
122 		b43_radio_write(dev, 0x060, 0x007f);  in b43_radio_2064_init()
123 		b43_radio_write(dev, 0x061, 0x0072);  in b43_radio_2064_init()
124 		b43_radio_write(dev, 0x062, 0x007f);  in b43_radio_2064_init()
126 	b43_radio_write(dev, 0x01d, 0x0002);  in b43_radio_2064_init()
127 	b43_radio_write(dev, 0x01e, 0x0006);  in b43_radio_2064_init()
129 	b43_phy_write(dev, 0x4ea, 0x4688);  in b43_radio_2064_init()
130 	b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);  in b43_radio_2064_init()
131 	b43_phy_mask(dev, 0x4eb, ~0x01c0);  in b43_radio_2064_init()
132 	b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);  in b43_radio_2064_init()
134 	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);  in b43_radio_2064_init()
136 	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);  in b43_radio_2064_init()
137 	b43_radio_set(dev, 0x004, 0x40);  in b43_radio_2064_init()
138 	b43_radio_set(dev, 0x120, 0x10);  in b43_radio_2064_init()
139 	b43_radio_set(dev, 0x078, 0x80);  in b43_radio_2064_init()
140 	b43_radio_set(dev, 0x129, 0x2);  in b43_radio_2064_init()
141 	b43_radio_set(dev, 0x057, 0x1);  in b43_radio_2064_init()
142 	b43_radio_set(dev, 0x05b, 0x2);  in b43_radio_2064_init()
145 	b43_radio_read(dev, 0x05c);  in b43_radio_2064_init()
147 	b43_radio_mask(dev, 0x05b, (u16) ~0xff02);  in b43_radio_2064_init()
148 	b43_radio_mask(dev, 0x057, (u16) ~0xff01);  in b43_radio_2064_init()
150 	b43_phy_write(dev, 0x933, 0x2d6b);  in b43_radio_2064_init()
151 	b43_phy_write(dev, 0x934, 0x2d6b);  in b43_radio_2064_init()
152 	b43_phy_write(dev, 0x935, 0x2d6b);  in b43_radio_2064_init()
153 	b43_phy_write(dev, 0x936, 0x2d6b);  in b43_radio_2064_init()
154 	b43_phy_write(dev, 0x937, 0x016b);  in b43_radio_2064_init()
156 	b43_radio_mask(dev, 0x057, (u16) ~0xff02);  in b43_radio_2064_init()
157 	b43_radio_write(dev, 0x0c2, 0x006f);  in b43_radio_2064_init()
165 static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)  in b43_phy_lcn_afe_set_unset()  argument
167 	u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);  in b43_phy_lcn_afe_set_unset()
168 	u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);  in b43_phy_lcn_afe_set_unset()
170 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);  in b43_phy_lcn_afe_set_unset()
171 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);  in b43_phy_lcn_afe_set_unset()
173 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);  in b43_phy_lcn_afe_set_unset()
174 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);  in b43_phy_lcn_afe_set_unset()
176 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);  in b43_phy_lcn_afe_set_unset()
177 	b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);  in b43_phy_lcn_afe_set_unset()
181 static u16 b43_phy_lcn_get_pa_gain(struct b43_wldev *dev)  in b43_phy_lcn_get_pa_gain()  argument
183 	return (b43_phy_read(dev, 0x4fb) & 0x7f00) >> 8;  in b43_phy_lcn_get_pa_gain()
187 static void b43_phy_lcn_set_dac_gain(struct b43_wldev *dev, u16 dac_gain)  in b43_phy_lcn_set_dac_gain()  argument
191 	dac_ctrl = b43_phy_read(dev, 0x439);  in b43_phy_lcn_set_dac_gain()
194 	b43_phy_maskset(dev, 0x439, ~0xfff, dac_ctrl);  in b43_phy_lcn_set_dac_gain()
198 static void b43_phy_lcn_set_bbmult(struct b43_wldev *dev, u8 m0)  in b43_phy_lcn_set_bbmult()  argument
200 	b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x57), m0 << 8);  in b43_phy_lcn_set_bbmult()
204 static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)  in b43_phy_lcn_clear_tx_power_offsets()  argument
209 		b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);  in b43_phy_lcn_clear_tx_power_offsets()
211 			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);  in b43_phy_lcn_clear_tx_power_offsets()
212 			b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);  in b43_phy_lcn_clear_tx_power_offsets()
216 	b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);  in b43_phy_lcn_clear_tx_power_offsets()
218 		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);  in b43_phy_lcn_clear_tx_power_offsets()
219 		b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);  in b43_phy_lcn_clear_tx_power_offsets()
224 static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)  in b43_phy_lcn_rev0_baseband_init()  argument
226 	b43_radio_write(dev, 0x11c, 0);  in b43_phy_lcn_rev0_baseband_init()
228 	b43_phy_write(dev, 0x43b, 0);  in b43_phy_lcn_rev0_baseband_init()
229 	b43_phy_write(dev, 0x43c, 0);  in b43_phy_lcn_rev0_baseband_init()
230 	b43_phy_write(dev, 0x44c, 0);  in b43_phy_lcn_rev0_baseband_init()
231 	b43_phy_write(dev, 0x4e6, 0);  in b43_phy_lcn_rev0_baseband_init()
232 	b43_phy_write(dev, 0x4f9, 0);  in b43_phy_lcn_rev0_baseband_init()
233 	b43_phy_write(dev, 0x4b0, 0);  in b43_phy_lcn_rev0_baseband_init()
234 	b43_phy_write(dev, 0x938, 0);  in b43_phy_lcn_rev0_baseband_init()
235 	b43_phy_write(dev, 0x4b0, 0);  in b43_phy_lcn_rev0_baseband_init()
236 	b43_phy_write(dev, 0x44e, 0);  in b43_phy_lcn_rev0_baseband_init()
238 	b43_phy_set(dev, 0x567, 0x03);  in b43_phy_lcn_rev0_baseband_init()
240 	b43_phy_set(dev, 0x44a, 0x44);  in b43_phy_lcn_rev0_baseband_init()
241 	b43_phy_write(dev, 0x44a, 0x80);  in b43_phy_lcn_rev0_baseband_init()
243 	if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))  in b43_phy_lcn_rev0_baseband_init()
245 	b43_phy_maskset(dev, 0x634, ~0xff, 0xc);  in b43_phy_lcn_rev0_baseband_init()
246 	if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {  in b43_phy_lcn_rev0_baseband_init()
247 		b43_phy_maskset(dev, 0x634, ~0xff, 0xa);  in b43_phy_lcn_rev0_baseband_init()
248 		b43_phy_write(dev, 0x910, 0x1);  in b43_phy_lcn_rev0_baseband_init()
251 	b43_phy_write(dev, 0x910, 0x1);  in b43_phy_lcn_rev0_baseband_init()
253 	b43_phy_maskset(dev, 0x448, ~0x300, 0x100);  in b43_phy_lcn_rev0_baseband_init()
254 	b43_phy_maskset(dev, 0x608, ~0xff, 0x17);  in b43_phy_lcn_rev0_baseband_init()
255 	b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);  in b43_phy_lcn_rev0_baseband_init()
259 static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)  in b43_phy_lcn_bu_tweaks()  argument
261 	b43_phy_set(dev, 0x805, 0x1);  in b43_phy_lcn_bu_tweaks()
263 	b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);  in b43_phy_lcn_bu_tweaks()
264 	b43_phy_maskset(dev, 0x030, ~0x7, 0x3);  in b43_phy_lcn_bu_tweaks()
266 	b43_phy_write(dev, 0x414, 0x1e10);  in b43_phy_lcn_bu_tweaks()
267 	b43_phy_write(dev, 0x415, 0x0640);  in b43_phy_lcn_bu_tweaks()
269 	b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);  in b43_phy_lcn_bu_tweaks()
271 	b43_phy_set(dev, 0x44a, 0x44);  in b43_phy_lcn_bu_tweaks()
272 	b43_phy_write(dev, 0x44a, 0x80);  in b43_phy_lcn_bu_tweaks()
274 	b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);  in b43_phy_lcn_bu_tweaks()
275 	b43_phy_maskset(dev, 0x420, ~0xff, 0x10);  in b43_phy_lcn_bu_tweaks()
277 	if (dev->dev->bus_sprom->board_rev >= 0x1204)  in b43_phy_lcn_bu_tweaks()
278 		b43_radio_set(dev, 0x09b, 0xf0);  in b43_phy_lcn_bu_tweaks()
280 	b43_phy_write(dev, 0x7d6, 0x0902);  in b43_phy_lcn_bu_tweaks()
282 	b43_phy_maskset(dev, 0x429, ~0xf, 0x9);  in b43_phy_lcn_bu_tweaks()
283 	b43_phy_maskset(dev, 0x429, ~(0x3f << 4), 0xe << 4);  in b43_phy_lcn_bu_tweaks()
285 	if (dev->phy.rev == 1) {  in b43_phy_lcn_bu_tweaks()
286 		b43_phy_maskset(dev, 0x423, ~0xff, 0x46);  in b43_phy_lcn_bu_tweaks()
287 		b43_phy_maskset(dev, 0x411, ~0xff, 1);  in b43_phy_lcn_bu_tweaks()
288 		b43_phy_set(dev, 0x434, 0xff); /* FIXME: update to wl */  in b43_phy_lcn_bu_tweaks()
292 		b43_phy_maskset(dev, 0x656, ~0xf, 2);  in b43_phy_lcn_bu_tweaks()
293 		b43_phy_set(dev, 0x44d, 4);  in b43_phy_lcn_bu_tweaks()
295 		b43_radio_set(dev, 0x0f7, 0x4);  in b43_phy_lcn_bu_tweaks()
296 		b43_radio_mask(dev, 0x0f1, ~0x3);  in b43_phy_lcn_bu_tweaks()
297 		b43_radio_maskset(dev, 0x0f2, ~0xf8, 0x90);  in b43_phy_lcn_bu_tweaks()
298 		b43_radio_maskset(dev, 0x0f3, ~0x3, 0x2);  in b43_phy_lcn_bu_tweaks()
299 		b43_radio_maskset(dev, 0x0f3, ~0xf0, 0xa0);  in b43_phy_lcn_bu_tweaks()
301 		b43_radio_set(dev, 0x11f, 0x2);  in b43_phy_lcn_bu_tweaks()
303 		b43_phy_lcn_clear_tx_power_offsets(dev);  in b43_phy_lcn_bu_tweaks()
310 static void b43_phy_lcn_sense_setup(struct b43_wldev *dev,  in b43_phy_lcn_sense_setup()  argument
334 		save_radio_regs[i][1] = b43_radio_read(dev,  in b43_phy_lcn_sense_setup()
337 		save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);  in b43_phy_lcn_sense_setup()
338 	b43_mac_suspend(dev);  in b43_phy_lcn_sense_setup()
339 	save_radio_4a4 = b43_radio_read(dev, 0x4a4);  in b43_phy_lcn_sense_setup()
341 	tx_pwr_idx = dev->phy.lcn->tx_pwr_curr_idx;  in b43_phy_lcn_sense_setup()
345 	b43_radio_set(dev, 0x007, 0x1);  in b43_phy_lcn_sense_setup()
346 	b43_radio_set(dev, 0x0ff, 0x10);  in b43_phy_lcn_sense_setup()
347 	b43_radio_set(dev, 0x11f, 0x4);  in b43_phy_lcn_sense_setup()
349 	b43_phy_mask(dev, 0x503, ~0x1);  in b43_phy_lcn_sense_setup()
350 	b43_phy_mask(dev, 0x503, ~0x4);  in b43_phy_lcn_sense_setup()
351 	b43_phy_mask(dev, 0x4a4, ~0x4000);  in b43_phy_lcn_sense_setup()
352 	b43_phy_mask(dev, 0x4a4, (u16) ~0x8000);  in b43_phy_lcn_sense_setup()
353 	b43_phy_mask(dev, 0x4d0, ~0x20);  in b43_phy_lcn_sense_setup()
354 	b43_phy_set(dev, 0x4a5, 0xff);  in b43_phy_lcn_sense_setup()
355 	b43_phy_maskset(dev, 0x4a5, ~0x7000, 0x5000);  in b43_phy_lcn_sense_setup()
356 	b43_phy_mask(dev, 0x4a5, ~0x700);  in b43_phy_lcn_sense_setup()
357 	b43_phy_maskset(dev, 0x40d, ~0xff, 64);  in b43_phy_lcn_sense_setup()
358 	b43_phy_maskset(dev, 0x40d, ~0x700, 0x600);  in b43_phy_lcn_sense_setup()
359 	b43_phy_maskset(dev, 0x4a2, ~0xff, 64);  in b43_phy_lcn_sense_setup()
360 	b43_phy_maskset(dev, 0x4a2, ~0x700, 0x600);  in b43_phy_lcn_sense_setup()
361 	b43_phy_maskset(dev, 0x4d9, ~0x70, 0x20);  in b43_phy_lcn_sense_setup()
362 	b43_phy_maskset(dev, 0x4d9, ~0x700, 0x300);  in b43_phy_lcn_sense_setup()
363 	b43_phy_maskset(dev, 0x4d9, ~0x7000, 0x1000);  in b43_phy_lcn_sense_setup()
364 	b43_phy_mask(dev, 0x4da, ~0x1000);  in b43_phy_lcn_sense_setup()
365 	b43_phy_set(dev, 0x4da, 0x2000);  in b43_phy_lcn_sense_setup()
366 	b43_phy_set(dev, 0x4a6, 0x8000);  in b43_phy_lcn_sense_setup()
368 	b43_radio_write(dev, 0x025, 0xc);  in b43_phy_lcn_sense_setup()
369 	b43_radio_set(dev, 0x005, 0x8);  in b43_phy_lcn_sense_setup()
370 	b43_phy_set(dev, 0x938, 0x4);  in b43_phy_lcn_sense_setup()
371 	b43_phy_set(dev, 0x939, 0x4);  in b43_phy_lcn_sense_setup()
372 	b43_phy_set(dev, 0x4a4, 0x1000);  in b43_phy_lcn_sense_setup()
375 	b43_lcntab_write(dev, B43_LCNTAB16(0x8, 0x6), 0x640);  in b43_phy_lcn_sense_setup()
379 		b43_phy_set(dev, 0x4d7, 0x8);  in b43_phy_lcn_sense_setup()
380 		b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x1000);  in b43_phy_lcn_sense_setup()
384 		b43_radio_set(dev, 0x082, 0x20);  in b43_phy_lcn_sense_setup()
387 		b43_phy_set(dev, 0x4d7, 0x8);  in b43_phy_lcn_sense_setup()
388 		b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x3000);  in b43_phy_lcn_sense_setup()
396 	b43_phy_set(dev, 0x4d8, 0x1);  in b43_phy_lcn_sense_setup()
397 	b43_phy_maskset(dev, 0x4d8, ~(0x3ff << 2), auxpga_vmid << 2);  in b43_phy_lcn_sense_setup()
398 	b43_phy_set(dev, 0x4d8, 0x2);  in b43_phy_lcn_sense_setup()
399 	b43_phy_maskset(dev, 0x4d8, ~(0x7 << 12), auxpga_gain << 12);  in b43_phy_lcn_sense_setup()
400 	b43_phy_set(dev, 0x4d0, 0x20);  in b43_phy_lcn_sense_setup()
401 	b43_radio_write(dev, 0x112, 0x6);  in b43_phy_lcn_sense_setup()
403 	b43_dummy_transmission(dev, true, false);  in b43_phy_lcn_sense_setup()
405 	if (!(b43_phy_read(dev, 0x476) & 0x8000))  in b43_phy_lcn_sense_setup()
410 		b43_radio_write(dev, save_radio_regs[i][0],  in b43_phy_lcn_sense_setup()
413 		b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);  in b43_phy_lcn_sense_setup()
415 	b43_radio_write(dev, 0x4a4, save_radio_4a4);  in b43_phy_lcn_sense_setup()
417 	b43_mac_enable(dev);  in b43_phy_lcn_sense_setup()
422 static bool b43_phy_lcn_load_tx_iir_cck_filter(struct b43_wldev *dev,  in b43_phy_lcn_load_tx_iir_cck_filter()  argument
465 				b43_phy_write(dev, phy_regs[j],  in b43_phy_lcn_load_tx_iir_cck_filter()
474 static bool b43_phy_lcn_load_tx_iir_ofdm_filter(struct b43_wldev *dev,  in b43_phy_lcn_load_tx_iir_ofdm_filter()  argument
493 				b43_phy_write(dev, phy_regs[j],  in b43_phy_lcn_load_tx_iir_ofdm_filter()
503 static void b43_phy_lcn_set_tx_gain_override(struct b43_wldev *dev, bool enable)  in b43_phy_lcn_set_tx_gain_override()  argument
505 	b43_phy_maskset(dev, 0x4b0, ~(0x1 << 7), enable << 7);  in b43_phy_lcn_set_tx_gain_override()
506 	b43_phy_maskset(dev, 0x4b0, ~(0x1 << 14), enable << 14);  in b43_phy_lcn_set_tx_gain_override()
507 	b43_phy_maskset(dev, 0x43b, ~(0x1 << 6), enable << 6);  in b43_phy_lcn_set_tx_gain_override()
511 static void b43_phy_lcn_set_tx_gain(struct b43_wldev *dev,  in b43_phy_lcn_set_tx_gain()  argument
514 	u16 pa_gain = b43_phy_lcn_get_pa_gain(dev);  in b43_phy_lcn_set_tx_gain()
516 	b43_phy_write(dev, 0x4b5,  in b43_phy_lcn_set_tx_gain()
518 	b43_phy_maskset(dev, 0x4fb, ~0x7fff,  in b43_phy_lcn_set_tx_gain()
520 	b43_phy_write(dev, 0x4fc,  in b43_phy_lcn_set_tx_gain()
522 	b43_phy_maskset(dev, 0x4fd, ~0x7fff,  in b43_phy_lcn_set_tx_gain()
525 	b43_phy_lcn_set_dac_gain(dev, target_gains->dac_gain);  in b43_phy_lcn_set_tx_gain()
526 	b43_phy_lcn_set_tx_gain_override(dev, true);  in b43_phy_lcn_set_tx_gain()
530 static void b43_phy_lcn_tx_pwr_ctl_init(struct b43_wldev *dev)  in b43_phy_lcn_tx_pwr_ctl_init()  argument
535 	b43_mac_suspend(dev);  in b43_phy_lcn_tx_pwr_ctl_init()
537 	if (!dev->phy.lcn->hw_pwr_ctl_capable) {  in b43_phy_lcn_tx_pwr_ctl_init()
538 		if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {  in b43_phy_lcn_tx_pwr_ctl_init()
551 		b43_phy_lcn_set_tx_gain(dev, &tx_gains);  in b43_phy_lcn_tx_pwr_ctl_init()
552 		b43_phy_lcn_set_bbmult(dev, bbmult);  in b43_phy_lcn_tx_pwr_ctl_init()
553 		b43_phy_lcn_sense_setup(dev, B43_SENSE_TEMP);  in b43_phy_lcn_tx_pwr_ctl_init()
555 		b43err(dev->wl, "TX power control not supported for this HW\n");  in b43_phy_lcn_tx_pwr_ctl_init()
558 	b43_mac_enable(dev);  in b43_phy_lcn_tx_pwr_ctl_init()
562 static void b43_phy_lcn_txrx_spur_avoidance_mode(struct b43_wldev *dev,  in b43_phy_lcn_txrx_spur_avoidance_mode()  argument
566 		b43_phy_write(dev, 0x942, 0x7);  in b43_phy_lcn_txrx_spur_avoidance_mode()
567 		b43_phy_write(dev, 0x93b, ((1 << 13) + 23));  in b43_phy_lcn_txrx_spur_avoidance_mode()
568 		b43_phy_write(dev, 0x93c, ((1 << 13) + 1989));  in b43_phy_lcn_txrx_spur_avoidance_mode()
570 		b43_phy_write(dev, 0x44a, 0x084);  in b43_phy_lcn_txrx_spur_avoidance_mode()
571 		b43_phy_write(dev, 0x44a, 0x080);  in b43_phy_lcn_txrx_spur_avoidance_mode()
572 		b43_phy_write(dev, 0x6d3, 0x2222);  in b43_phy_lcn_txrx_spur_avoidance_mode()
573 		b43_phy_write(dev, 0x6d3, 0x2220);  in b43_phy_lcn_txrx_spur_avoidance_mode()
575 		b43_phy_write(dev, 0x942, 0x0);  in b43_phy_lcn_txrx_spur_avoidance_mode()
576 		b43_phy_write(dev, 0x93b, ((0 << 13) + 23));  in b43_phy_lcn_txrx_spur_avoidance_mode()
577 		b43_phy_write(dev, 0x93c, ((0 << 13) + 1989));  in b43_phy_lcn_txrx_spur_avoidance_mode()
579 	b43_mac_switch_freq(dev, enable);  in b43_phy_lcn_txrx_spur_avoidance_mode()
587 static void b43_phy_lcn_set_channel_tweaks(struct b43_wldev *dev, int channel)  in b43_phy_lcn_set_channel_tweaks()  argument
589 	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;  in b43_phy_lcn_set_channel_tweaks()
591 	b43_phy_maskset(dev, 0x448, ~0x300, (channel == 14) ? 0x200 : 0x100);  in b43_phy_lcn_set_channel_tweaks()
601 		b43_phy_write(dev, 0x942, 0);  in b43_phy_lcn_set_channel_tweaks()
603 		b43_phy_lcn_txrx_spur_avoidance_mode(dev, false);  in b43_phy_lcn_set_channel_tweaks()
604 		b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1b00);  in b43_phy_lcn_set_channel_tweaks()
605 		b43_phy_write(dev, 0x425, 0x5907);  in b43_phy_lcn_set_channel_tweaks()
613 		b43_phy_write(dev, 0x942, 0);  in b43_phy_lcn_set_channel_tweaks()
615 		b43_phy_lcn_txrx_spur_avoidance_mode(dev, true);  in b43_phy_lcn_set_channel_tweaks()
616 		b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1f00);  in b43_phy_lcn_set_channel_tweaks()
617 		b43_phy_write(dev, 0x425, 0x590a);  in b43_phy_lcn_set_channel_tweaks()
620 	b43_phy_set(dev, 0x44a, 0x44);  in b43_phy_lcn_set_channel_tweaks()
621 	b43_phy_write(dev, 0x44a, 0x80);  in b43_phy_lcn_set_channel_tweaks()
625 static int b43_phy_lcn_set_channel(struct b43_wldev *dev,  in b43_phy_lcn_set_channel()  argument
635 	b43_phy_lcn_set_channel_tweaks(dev, channel->hw_value);  in b43_phy_lcn_set_channel()
637 	b43_phy_set(dev, 0x44a, 0x44);  in b43_phy_lcn_set_channel()
638 	b43_phy_write(dev, 0x44a, 0x80);  in b43_phy_lcn_set_channel()
640 	b43_radio_2064_channel_setup(dev);  in b43_phy_lcn_set_channel()
643 	b43_phy_lcn_afe_set_unset(dev);  in b43_phy_lcn_set_channel()
645 	b43_phy_write(dev, 0x657, sfo_cfg[channel->hw_value - 1][0]);  in b43_phy_lcn_set_channel()
646 	b43_phy_write(dev, 0x658, sfo_cfg[channel->hw_value - 1][1]);  in b43_phy_lcn_set_channel()
649 		b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (2) << 8);  in b43_phy_lcn_set_channel()
650 		b43_phy_lcn_load_tx_iir_cck_filter(dev, 3);  in b43_phy_lcn_set_channel()
652 		b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (1) << 8);  in b43_phy_lcn_set_channel()
654 		b43_phy_lcn_load_tx_iir_cck_filter(dev, 25);  in b43_phy_lcn_set_channel()
657 	b43_phy_lcn_load_tx_iir_ofdm_filter(dev, 0);  in b43_phy_lcn_set_channel()
659 	b43_phy_maskset(dev, 0x4eb, ~(0x7 << 3), 0x1 << 3);  in b43_phy_lcn_set_channel()
668 static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)  in b43_phy_lcn_op_allocate()  argument
675 	dev->phy.lcn = phy_lcn;  in b43_phy_lcn_op_allocate()
680 static void b43_phy_lcn_op_free(struct b43_wldev *dev)  in b43_phy_lcn_op_free()  argument
682 	struct b43_phy *phy = &dev->phy;  in b43_phy_lcn_op_free()
689 static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)  in b43_phy_lcn_op_prepare_structs()  argument
691 	struct b43_phy *phy = &dev->phy;  in b43_phy_lcn_op_prepare_structs()
698 static int b43_phy_lcn_op_init(struct b43_wldev *dev)  in b43_phy_lcn_op_init()  argument
700 	struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;  in b43_phy_lcn_op_init()
702 	b43_phy_set(dev, 0x44a, 0x80);  in b43_phy_lcn_op_init()
703 	b43_phy_mask(dev, 0x44a, 0x7f);  in b43_phy_lcn_op_init()
704 	b43_phy_set(dev, 0x6d1, 0x80);  in b43_phy_lcn_op_init()
705 	b43_phy_write(dev, 0x6d0, 0x7);  in b43_phy_lcn_op_init()
707 	b43_phy_lcn_afe_set_unset(dev);  in b43_phy_lcn_op_init()
709 	b43_phy_write(dev, 0x60a, 0xa0);  in b43_phy_lcn_op_init()
710 	b43_phy_write(dev, 0x46a, 0x19);  in b43_phy_lcn_op_init()
711 	b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);  in b43_phy_lcn_op_init()
713 	b43_phy_lcn_tables_init(dev);  in b43_phy_lcn_op_init()
715 	b43_phy_lcn_rev0_baseband_init(dev);  in b43_phy_lcn_op_init()
716 	b43_phy_lcn_bu_tweaks(dev);  in b43_phy_lcn_op_init()
718 	if (dev->phy.radio_ver == 0x2064)  in b43_phy_lcn_op_init()
719 		b43_radio_2064_init(dev);  in b43_phy_lcn_op_init()
723 	if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)  in b43_phy_lcn_op_init()
724 		b43_phy_lcn_tx_pwr_ctl_init(dev);  in b43_phy_lcn_op_init()
726 	b43_switch_channel(dev, dev->phy.channel);  in b43_phy_lcn_op_init()
733 	b43_phy_set(dev, 0x448, 0x4000);  in b43_phy_lcn_op_init()
735 	b43_phy_mask(dev, 0x448, ~0x4000);  in b43_phy_lcn_op_init()
742 static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,  in b43_phy_lcn_op_software_rfkill()  argument
745 	if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)  in b43_phy_lcn_op_software_rfkill()
746 		b43err(dev->wl, "MAC not suspended\n");  in b43_phy_lcn_op_software_rfkill()
749 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);  in b43_phy_lcn_op_software_rfkill()
750 		b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);  in b43_phy_lcn_op_software_rfkill()
752 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);  in b43_phy_lcn_op_software_rfkill()
753 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);  in b43_phy_lcn_op_software_rfkill()
754 		b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);  in b43_phy_lcn_op_software_rfkill()
756 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);  in b43_phy_lcn_op_software_rfkill()
757 		b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);  in b43_phy_lcn_op_software_rfkill()
759 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);  in b43_phy_lcn_op_software_rfkill()
760 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);  in b43_phy_lcn_op_software_rfkill()
761 		b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);  in b43_phy_lcn_op_software_rfkill()
765 static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)  in b43_phy_lcn_op_switch_analog()  argument
768 		b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);  in b43_phy_lcn_op_switch_analog()
770 		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);  in b43_phy_lcn_op_switch_analog()
771 		b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);  in b43_phy_lcn_op_switch_analog()
775 static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,  in b43_phy_lcn_op_switch_channel()  argument
778 	struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;  in b43_phy_lcn_op_switch_channel()
780 		cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);  in b43_phy_lcn_op_switch_channel()
782 	if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {  in b43_phy_lcn_op_switch_channel()
789 	return b43_phy_lcn_set_channel(dev, channel, channel_type);  in b43_phy_lcn_op_switch_channel()
792 static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)  in b43_phy_lcn_op_get_default_chan()  argument
794 	if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)  in b43_phy_lcn_op_get_default_chan()
800 b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)  in b43_phy_lcn_op_recalc_txpower()  argument
805 static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)  in b43_phy_lcn_op_adjust_txpower()  argument
813 static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,  in b43_phy_lcn_op_maskset()  argument
816 	b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);  in b43_phy_lcn_op_maskset()
817 	b43_write16(dev, B43_MMIO_PHY_DATA,  in b43_phy_lcn_op_maskset()
818 		    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);  in b43_phy_lcn_op_maskset()
821 static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)  in b43_phy_lcn_op_radio_read()  argument
826 	b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);  in b43_phy_lcn_op_radio_read()
827 	return b43_read16(dev, B43_MMIO_RADIO24_DATA);  in b43_phy_lcn_op_radio_read()
830 static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,  in b43_phy_lcn_op_radio_write()  argument
833 	b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);  in b43_phy_lcn_op_radio_write()
834 	b43_write16(dev, B43_MMIO_RADIO24_DATA, value);  in b43_phy_lcn_op_radio_write()