Lines Matching +full:0 +full:- +full:dev
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
8 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
9 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
41 5, -7, -20, -20,
42 -20, -20, -20, -20,
43 -20, -20, -20, -20,
54 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
65 return b43_radio_channel_codes_bg[channel - 1]; in channel2freq_bg()
68 static void generate_rfatt_list(struct b43_wldev *dev, in generate_rfatt_list() argument
71 struct b43_phy *phy = &dev->phy; in generate_rfatt_list()
75 {.att = 3,.with_padmix = 0,}, in generate_rfatt_list()
76 {.att = 1,.with_padmix = 0,}, in generate_rfatt_list()
77 {.att = 5,.with_padmix = 0,}, in generate_rfatt_list()
78 {.att = 7,.with_padmix = 0,}, in generate_rfatt_list()
79 {.att = 9,.with_padmix = 0,}, in generate_rfatt_list()
80 {.att = 2,.with_padmix = 0,}, in generate_rfatt_list()
81 {.att = 0,.with_padmix = 0,}, in generate_rfatt_list()
82 {.att = 4,.with_padmix = 0,}, in generate_rfatt_list()
83 {.att = 6,.with_padmix = 0,}, in generate_rfatt_list()
84 {.att = 8,.with_padmix = 0,}, in generate_rfatt_list()
90 /* Radio.rev == 8 && Radio.version == 0x2050 */ in generate_rfatt_list()
102 {.att = 0,.with_padmix = 1,}, in generate_rfatt_list()
111 if (!b43_has_hardware_pctl(dev)) { in generate_rfatt_list()
113 list->list = rfatt_0; in generate_rfatt_list()
114 list->len = ARRAY_SIZE(rfatt_0); in generate_rfatt_list()
115 list->min_val = 0; in generate_rfatt_list()
116 list->max_val = 9; in generate_rfatt_list()
119 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { in generate_rfatt_list()
121 list->list = rfatt_1; in generate_rfatt_list()
122 list->len = ARRAY_SIZE(rfatt_1); in generate_rfatt_list()
123 list->min_val = 0; in generate_rfatt_list()
124 list->max_val = 14; in generate_rfatt_list()
128 list->list = rfatt_2; in generate_rfatt_list()
129 list->len = ARRAY_SIZE(rfatt_2); in generate_rfatt_list()
130 list->min_val = 0; in generate_rfatt_list()
131 list->max_val = 9; in generate_rfatt_list()
134 static void generate_bbatt_list(struct b43_wldev *dev, in generate_bbatt_list() argument
138 {.att = 0,}, in generate_bbatt_list()
149 list->list = bbatt_0; in generate_bbatt_list()
150 list->len = ARRAY_SIZE(bbatt_0); in generate_bbatt_list()
151 list->min_val = 0; in generate_bbatt_list()
152 list->max_val = 8; in generate_bbatt_list()
155 static void b43_shm_clear_tssi(struct b43_wldev *dev) in b43_shm_clear_tssi() argument
157 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F); in b43_shm_clear_tssi()
158 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F); in b43_shm_clear_tssi()
159 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F); in b43_shm_clear_tssi()
160 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F); in b43_shm_clear_tssi()
164 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel) in b43_synth_pu_workaround() argument
166 struct b43_phy *phy = &dev->phy; in b43_synth_pu_workaround()
170 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) { in b43_synth_pu_workaround()
176 b43_write16(dev, B43_MMIO_CHANNEL, in b43_synth_pu_workaround()
179 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1)); in b43_synth_pu_workaround()
182 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_synth_pu_workaround()
186 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, in b43_gphy_set_baseband_attenuation() argument
189 struct b43_phy *phy = &dev->phy; in b43_gphy_set_baseband_attenuation()
191 if (phy->analog == 0) { in b43_gphy_set_baseband_attenuation()
192 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0) in b43_gphy_set_baseband_attenuation()
193 & 0xFFF0) | in b43_gphy_set_baseband_attenuation()
195 } else if (phy->analog > 1) { in b43_gphy_set_baseband_attenuation()
196 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2)); in b43_gphy_set_baseband_attenuation()
198 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3)); in b43_gphy_set_baseband_attenuation()
202 /* Adjust the transmission power output (G-PHY) */
203 static void b43_set_txpower_g(struct b43_wldev *dev, in b43_set_txpower_g() argument
207 struct b43_phy *phy = &dev->phy; in b43_set_txpower_g()
208 struct b43_phy_g *gphy = phy->g; in b43_set_txpower_g()
209 struct b43_txpower_lo_control *lo = gphy->lo_control; in b43_set_txpower_g()
213 bb = bbatt->att; in b43_set_txpower_g()
214 rf = rfatt->att; in b43_set_txpower_g()
215 tx_bias = lo->tx_bias; in b43_set_txpower_g()
216 tx_magn = lo->tx_magn; in b43_set_txpower_g()
217 if (unlikely(tx_bias == 0xFF)) in b43_set_txpower_g()
218 tx_bias = 0; in b43_set_txpower_g()
221 * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */ in b43_set_txpower_g()
222 gphy->tx_control = tx_control; in b43_set_txpower_g()
223 memmove(&gphy->rfatt, rfatt, sizeof(*rfatt)); in b43_set_txpower_g()
224 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX); in b43_set_txpower_g()
225 memmove(&gphy->bbatt, bbatt, sizeof(*bbatt)); in b43_set_txpower_g()
227 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_set_txpower_g()
228 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), " in b43_set_txpower_g()
229 "rfatt(%u), tx_control(0x%02X), " in b43_set_txpower_g()
230 "tx_bias(0x%02X), tx_magn(0x%02X)\n", in b43_set_txpower_g()
234 b43_gphy_set_baseband_attenuation(dev, bb); in b43_set_txpower_g()
235 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf); in b43_set_txpower_g()
236 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { in b43_set_txpower_g()
237 b43_radio_write16(dev, 0x43, in b43_set_txpower_g()
238 (rf & 0x000F) | (tx_control & 0x0070)); in b43_set_txpower_g()
240 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F)); in b43_set_txpower_g()
241 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070)); in b43_set_txpower_g()
244 b43_radio_write16(dev, 0x52, tx_magn | tx_bias); in b43_set_txpower_g()
246 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F)); in b43_set_txpower_g()
248 b43_lo_g_adjust(dev); in b43_set_txpower_g()
252 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev) in b43_gphy_tssi_power_lt_init() argument
254 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_tssi_power_lt_init()
258 for (i = 0; i < 32; i++) in b43_gphy_tssi_power_lt_init()
259 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
261 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]); in b43_gphy_tssi_power_lt_init()
262 for (i = 0; i < 64; i += 2) { in b43_gphy_tssi_power_lt_init()
263 value = (u16) gphy->tssi2dbm[i]; in b43_gphy_tssi_power_lt_init()
264 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8; in b43_gphy_tssi_power_lt_init()
265 b43_phy_write(dev, 0x380 + (i / 2), value); in b43_gphy_tssi_power_lt_init()
270 static void b43_gphy_gain_lt_init(struct b43_wldev *dev) in b43_gphy_gain_lt_init() argument
272 struct b43_phy *phy = &dev->phy; in b43_gphy_gain_lt_init()
273 struct b43_phy_g *gphy = phy->g; in b43_gphy_gain_lt_init()
274 struct b43_txpower_lo_control *lo = gphy->lo_control; in b43_gphy_gain_lt_init()
275 u16 nr_written = 0; in b43_gphy_gain_lt_init()
279 for (rf = 0; rf < lo->rfatt_list.len; rf++) { in b43_gphy_gain_lt_init()
280 for (bb = 0; bb < lo->bbatt_list.len; bb++) { in b43_gphy_gain_lt_init()
281 if (nr_written >= 0x40) in b43_gphy_gain_lt_init()
283 tmp = lo->bbatt_list.list[bb].att; in b43_gphy_gain_lt_init()
285 if (phy->radio_rev == 8) in b43_gphy_gain_lt_init()
286 tmp |= 0x50; in b43_gphy_gain_lt_init()
288 tmp |= 0x40; in b43_gphy_gain_lt_init()
289 tmp |= lo->rfatt_list.list[rf].att; in b43_gphy_gain_lt_init()
290 b43_phy_write(dev, 0x3C0 + nr_written, tmp); in b43_gphy_gain_lt_init()
296 static void b43_set_all_gains(struct b43_wldev *dev, in b43_set_all_gains() argument
299 struct b43_phy *phy = &dev->phy; in b43_set_all_gains()
301 u16 start = 0x08, end = 0x18; in b43_set_all_gains()
305 if (phy->rev <= 1) { in b43_set_all_gains()
306 start = 0x10; in b43_set_all_gains()
307 end = 0x20; in b43_set_all_gains()
311 if (phy->rev <= 1) in b43_set_all_gains()
313 for (i = 0; i < 4; i++) in b43_set_all_gains()
314 b43_ofdmtab_write16(dev, table, i, first); in b43_set_all_gains()
317 b43_ofdmtab_write16(dev, table, i, second); in b43_set_all_gains()
319 if (third != -1) { in b43_set_all_gains()
321 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp); in b43_set_all_gains()
322 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp); in b43_set_all_gains()
323 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp); in b43_set_all_gains()
325 b43_dummy_transmission(dev, false, true); in b43_set_all_gains()
328 static void b43_set_original_gains(struct b43_wldev *dev) in b43_set_original_gains() argument
330 struct b43_phy *phy = &dev->phy; in b43_set_original_gains()
333 u16 start = 0x0008, end = 0x0018; in b43_set_original_gains()
335 if (phy->rev <= 1) { in b43_set_original_gains()
336 start = 0x0010; in b43_set_original_gains()
337 end = 0x0020; in b43_set_original_gains()
341 if (phy->rev <= 1) in b43_set_original_gains()
343 for (i = 0; i < 4; i++) { in b43_set_original_gains()
344 tmp = (i & 0xFFFC); in b43_set_original_gains()
345 tmp |= (i & 0x0001) << 1; in b43_set_original_gains()
346 tmp |= (i & 0x0002) >> 1; in b43_set_original_gains()
348 b43_ofdmtab_write16(dev, table, i, tmp); in b43_set_original_gains()
352 b43_ofdmtab_write16(dev, table, i, i - start); in b43_set_original_gains()
354 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040); in b43_set_original_gains()
355 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040); in b43_set_original_gains()
356 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000); in b43_set_original_gains()
357 b43_dummy_transmission(dev, false, true); in b43_set_original_gains()
360 /* https://bcm-specs.sipsolutions.net/NRSSILookupTable */
361 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) in b43_nrssi_hw_write() argument
363 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_write()
364 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); in b43_nrssi_hw_write()
367 /* https://bcm-specs.sipsolutions.net/NRSSILookupTable */
368 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset) in b43_nrssi_hw_read() argument
372 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); in b43_nrssi_hw_read()
373 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); in b43_nrssi_hw_read()
378 /* https://bcm-specs.sipsolutions.net/NRSSILookupTable */
379 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) in b43_nrssi_hw_update() argument
384 for (i = 0; i < 64; i++) { in b43_nrssi_hw_update()
385 tmp = b43_nrssi_hw_read(dev, i); in b43_nrssi_hw_update()
386 tmp -= val; in b43_nrssi_hw_update()
387 tmp = clamp_val(tmp, -32, 31); in b43_nrssi_hw_update()
388 b43_nrssi_hw_write(dev, i, tmp); in b43_nrssi_hw_update()
392 /* https://bcm-specs.sipsolutions.net/NRSSILookupTable */
393 static void b43_nrssi_mem_update(struct b43_wldev *dev) in b43_nrssi_mem_update() argument
395 struct b43_phy_g *gphy = dev->phy.g; in b43_nrssi_mem_update()
399 delta = 0x1F - gphy->nrssi[0]; in b43_nrssi_mem_update()
400 for (i = 0; i < 64; i++) { in b43_nrssi_mem_update()
401 tmp = (i - delta) * gphy->nrssislope; in b43_nrssi_mem_update()
402 tmp /= 0x10000; in b43_nrssi_mem_update()
403 tmp += 0x3A; in b43_nrssi_mem_update()
404 tmp = clamp_val(tmp, 0, 0x3F); in b43_nrssi_mem_update()
405 gphy->nrssi_lt[i] = tmp; in b43_nrssi_mem_update()
409 static void b43_calc_nrssi_offset(struct b43_wldev *dev) in b43_calc_nrssi_offset() argument
411 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_offset()
412 u16 backup[20] = { 0 }; in b43_calc_nrssi_offset()
415 u16 saved = 0xFFFF; in b43_calc_nrssi_offset()
417 backup[0] = b43_phy_read(dev, 0x0001); in b43_calc_nrssi_offset()
418 backup[1] = b43_phy_read(dev, 0x0811); in b43_calc_nrssi_offset()
419 backup[2] = b43_phy_read(dev, 0x0812); in b43_calc_nrssi_offset()
420 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_nrssi_offset()
421 backup[3] = b43_phy_read(dev, 0x0814); in b43_calc_nrssi_offset()
422 backup[4] = b43_phy_read(dev, 0x0815); in b43_calc_nrssi_offset()
424 backup[5] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_offset()
425 backup[6] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_offset()
426 backup[7] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_offset()
427 backup[8] = b43_phy_read(dev, 0x000A); in b43_calc_nrssi_offset()
428 backup[9] = b43_phy_read(dev, 0x0003); in b43_calc_nrssi_offset()
429 backup[10] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_offset()
430 backup[11] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_offset()
432 b43_phy_mask(dev, 0x0429, 0x7FFF); in b43_calc_nrssi_offset()
433 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000); in b43_calc_nrssi_offset()
434 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
435 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004); in b43_calc_nrssi_offset()
436 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); in b43_calc_nrssi_offset()
437 if (phy->rev >= 6) { in b43_calc_nrssi_offset()
438 backup[12] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_offset()
439 backup[13] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_offset()
440 backup[14] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_offset()
441 backup[15] = b43_phy_read(dev, 0x0810); in b43_calc_nrssi_offset()
442 backup[16] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_offset()
443 backup[17] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_offset()
444 backup[18] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_offset()
445 backup[19] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_offset()
447 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_offset()
448 b43_phy_write(dev, 0x002F, 0); in b43_calc_nrssi_offset()
449 b43_phy_write(dev, 0x080F, 0); in b43_calc_nrssi_offset()
450 b43_phy_write(dev, 0x0810, 0); in b43_calc_nrssi_offset()
451 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_offset()
452 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_offset()
453 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_offset()
454 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_offset()
456 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_offset()
457 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_offset()
460 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
461 if (v47F >= 0x20) in b43_calc_nrssi_offset()
462 v47F -= 0x40; in b43_calc_nrssi_offset()
464 for (i = 7; i >= 4; i--) { in b43_calc_nrssi_offset()
465 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
468 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
469 if (v47F >= 0x20) in b43_calc_nrssi_offset()
470 v47F -= 0x40; in b43_calc_nrssi_offset()
471 if (v47F < 31 && saved == 0xFFFF) in b43_calc_nrssi_offset()
474 if (saved == 0xFFFF) in b43_calc_nrssi_offset()
477 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_offset()
478 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_nrssi_offset()
479 b43_phy_set(dev, 0x0814, 0x0001); in b43_calc_nrssi_offset()
480 b43_phy_mask(dev, 0x0815, 0xFFFE); in b43_calc_nrssi_offset()
482 b43_phy_set(dev, 0x0811, 0x000C); in b43_calc_nrssi_offset()
483 b43_phy_set(dev, 0x0812, 0x000C); in b43_calc_nrssi_offset()
484 b43_phy_set(dev, 0x0811, 0x0030); in b43_calc_nrssi_offset()
485 b43_phy_set(dev, 0x0812, 0x0030); in b43_calc_nrssi_offset()
486 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_offset()
487 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_offset()
488 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_offset()
489 if (phy->rev == 0) { in b43_calc_nrssi_offset()
490 b43_phy_write(dev, 0x0003, 0x0122); in b43_calc_nrssi_offset()
492 b43_phy_set(dev, 0x000A, 0x2000); in b43_calc_nrssi_offset()
494 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_nrssi_offset()
495 b43_phy_set(dev, 0x0814, 0x0004); in b43_calc_nrssi_offset()
496 b43_phy_mask(dev, 0x0815, 0xFFFB); in b43_calc_nrssi_offset()
498 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_offset()
499 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_offset()
500 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_offset()
501 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F); in b43_calc_nrssi_offset()
503 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_offset()
504 if (v47F >= 0x20) in b43_calc_nrssi_offset()
505 v47F -= 0x40; in b43_calc_nrssi_offset()
506 if (v47F == -32) { in b43_calc_nrssi_offset()
507 for (i = 0; i < 4; i++) { in b43_calc_nrssi_offset()
508 b43_radio_write16(dev, 0x007B, i); in b43_calc_nrssi_offset()
511 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & in b43_calc_nrssi_offset()
512 0x003F); in b43_calc_nrssi_offset()
513 if (v47F >= 0x20) in b43_calc_nrssi_offset()
514 v47F -= 0x40; in b43_calc_nrssi_offset()
515 if (v47F > -31 && saved == 0xFFFF) in b43_calc_nrssi_offset()
518 if (saved == 0xFFFF) in b43_calc_nrssi_offset()
521 saved = 0; in b43_calc_nrssi_offset()
523 b43_radio_write16(dev, 0x007B, saved); in b43_calc_nrssi_offset()
525 if (phy->rev >= 6) { in b43_calc_nrssi_offset()
526 b43_phy_write(dev, 0x002E, backup[12]); in b43_calc_nrssi_offset()
527 b43_phy_write(dev, 0x002F, backup[13]); in b43_calc_nrssi_offset()
528 b43_phy_write(dev, 0x080F, backup[14]); in b43_calc_nrssi_offset()
529 b43_phy_write(dev, 0x0810, backup[15]); in b43_calc_nrssi_offset()
531 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_nrssi_offset()
532 b43_phy_write(dev, 0x0814, backup[3]); in b43_calc_nrssi_offset()
533 b43_phy_write(dev, 0x0815, backup[4]); in b43_calc_nrssi_offset()
535 b43_phy_write(dev, 0x005A, backup[5]); in b43_calc_nrssi_offset()
536 b43_phy_write(dev, 0x0059, backup[6]); in b43_calc_nrssi_offset()
537 b43_phy_write(dev, 0x0058, backup[7]); in b43_calc_nrssi_offset()
538 b43_phy_write(dev, 0x000A, backup[8]); in b43_calc_nrssi_offset()
539 b43_phy_write(dev, 0x0003, backup[9]); in b43_calc_nrssi_offset()
540 b43_radio_write16(dev, 0x0043, backup[11]); in b43_calc_nrssi_offset()
541 b43_radio_write16(dev, 0x007A, backup[10]); in b43_calc_nrssi_offset()
542 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2); in b43_calc_nrssi_offset()
543 b43_phy_set(dev, 0x0429, 0x8000); in b43_calc_nrssi_offset()
544 b43_set_original_gains(dev); in b43_calc_nrssi_offset()
545 if (phy->rev >= 6) { in b43_calc_nrssi_offset()
546 b43_phy_write(dev, 0x0801, backup[16]); in b43_calc_nrssi_offset()
547 b43_phy_write(dev, 0x0060, backup[17]); in b43_calc_nrssi_offset()
548 b43_phy_write(dev, 0x0014, backup[18]); in b43_calc_nrssi_offset()
549 b43_phy_write(dev, 0x0478, backup[19]); in b43_calc_nrssi_offset()
551 b43_phy_write(dev, 0x0001, backup[0]); in b43_calc_nrssi_offset()
552 b43_phy_write(dev, 0x0812, backup[2]); in b43_calc_nrssi_offset()
553 b43_phy_write(dev, 0x0811, backup[1]); in b43_calc_nrssi_offset()
556 static void b43_calc_nrssi_slope(struct b43_wldev *dev) in b43_calc_nrssi_slope() argument
558 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_slope()
559 struct b43_phy_g *gphy = phy->g; in b43_calc_nrssi_slope()
560 u16 backup[18] = { 0 }; in b43_calc_nrssi_slope()
564 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_calc_nrssi_slope()
566 if (phy->radio_rev >= 9) in b43_calc_nrssi_slope()
568 if (phy->radio_rev == 8) in b43_calc_nrssi_slope()
569 b43_calc_nrssi_offset(dev); in b43_calc_nrssi_slope()
571 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_calc_nrssi_slope()
572 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_calc_nrssi_slope()
573 backup[7] = b43_read16(dev, 0x03E2); in b43_calc_nrssi_slope()
574 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); in b43_calc_nrssi_slope()
575 backup[0] = b43_radio_read16(dev, 0x007A); in b43_calc_nrssi_slope()
576 backup[1] = b43_radio_read16(dev, 0x0052); in b43_calc_nrssi_slope()
577 backup[2] = b43_radio_read16(dev, 0x0043); in b43_calc_nrssi_slope()
578 backup[3] = b43_phy_read(dev, 0x0015); in b43_calc_nrssi_slope()
579 backup[4] = b43_phy_read(dev, 0x005A); in b43_calc_nrssi_slope()
580 backup[5] = b43_phy_read(dev, 0x0059); in b43_calc_nrssi_slope()
581 backup[6] = b43_phy_read(dev, 0x0058); in b43_calc_nrssi_slope()
582 backup[8] = b43_read16(dev, 0x03E6); in b43_calc_nrssi_slope()
583 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT); in b43_calc_nrssi_slope()
584 if (phy->rev >= 3) { in b43_calc_nrssi_slope()
585 backup[10] = b43_phy_read(dev, 0x002E); in b43_calc_nrssi_slope()
586 backup[11] = b43_phy_read(dev, 0x002F); in b43_calc_nrssi_slope()
587 backup[12] = b43_phy_read(dev, 0x080F); in b43_calc_nrssi_slope()
588 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL); in b43_calc_nrssi_slope()
589 backup[14] = b43_phy_read(dev, 0x0801); in b43_calc_nrssi_slope()
590 backup[15] = b43_phy_read(dev, 0x0060); in b43_calc_nrssi_slope()
591 backup[16] = b43_phy_read(dev, 0x0014); in b43_calc_nrssi_slope()
592 backup[17] = b43_phy_read(dev, 0x0478); in b43_calc_nrssi_slope()
593 b43_phy_write(dev, 0x002E, 0); in b43_calc_nrssi_slope()
594 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0); in b43_calc_nrssi_slope()
595 switch (phy->rev) { in b43_calc_nrssi_slope()
599 b43_phy_set(dev, 0x0478, 0x0100); in b43_calc_nrssi_slope()
600 b43_phy_set(dev, 0x0801, 0x0040); in b43_calc_nrssi_slope()
604 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_calc_nrssi_slope()
607 b43_phy_set(dev, 0x0060, 0x0040); in b43_calc_nrssi_slope()
608 b43_phy_set(dev, 0x0014, 0x0200); in b43_calc_nrssi_slope()
610 b43_radio_set(dev, 0x007A, 0x0070); in b43_calc_nrssi_slope()
611 b43_set_all_gains(dev, 0, 8, 0); in b43_calc_nrssi_slope()
612 b43_radio_mask(dev, 0x007A, 0x00F7); in b43_calc_nrssi_slope()
613 if (phy->rev >= 2) { in b43_calc_nrssi_slope()
614 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030); in b43_calc_nrssi_slope()
615 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010); in b43_calc_nrssi_slope()
617 b43_radio_set(dev, 0x007A, 0x0080); in b43_calc_nrssi_slope()
620 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
621 if (nrssi0 >= 0x0020) in b43_calc_nrssi_slope()
622 nrssi0 -= 0x0040; in b43_calc_nrssi_slope()
624 b43_radio_mask(dev, 0x007A, 0x007F); in b43_calc_nrssi_slope()
625 if (phy->rev >= 2) { in b43_calc_nrssi_slope()
626 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); in b43_calc_nrssi_slope()
629 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_calc_nrssi_slope()
630 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_calc_nrssi_slope()
631 | 0x2000); in b43_calc_nrssi_slope()
632 b43_radio_set(dev, 0x007A, 0x000F); in b43_calc_nrssi_slope()
633 b43_phy_write(dev, 0x0015, 0xF330); in b43_calc_nrssi_slope()
634 if (phy->rev >= 2) { in b43_calc_nrssi_slope()
635 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
636 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020); in b43_calc_nrssi_slope()
639 b43_set_all_gains(dev, 3, 0, 1); in b43_calc_nrssi_slope()
640 if (phy->radio_rev == 8) { in b43_calc_nrssi_slope()
641 b43_radio_write16(dev, 0x0043, 0x001F); in b43_calc_nrssi_slope()
643 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F; in b43_calc_nrssi_slope()
644 b43_radio_write16(dev, 0x0052, tmp | 0x0060); in b43_calc_nrssi_slope()
645 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0; in b43_calc_nrssi_slope()
646 b43_radio_write16(dev, 0x0043, tmp | 0x0009); in b43_calc_nrssi_slope()
648 b43_phy_write(dev, 0x005A, 0x0480); in b43_calc_nrssi_slope()
649 b43_phy_write(dev, 0x0059, 0x0810); in b43_calc_nrssi_slope()
650 b43_phy_write(dev, 0x0058, 0x000D); in b43_calc_nrssi_slope()
652 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); in b43_calc_nrssi_slope()
653 if (nrssi1 >= 0x0020) in b43_calc_nrssi_slope()
654 nrssi1 -= 0x0040; in b43_calc_nrssi_slope()
656 gphy->nrssislope = 0x00010000; in b43_calc_nrssi_slope()
658 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1); in b43_calc_nrssi_slope()
659 if (nrssi0 >= -4) { in b43_calc_nrssi_slope()
660 gphy->nrssi[0] = nrssi1; in b43_calc_nrssi_slope()
661 gphy->nrssi[1] = nrssi0; in b43_calc_nrssi_slope()
663 if (phy->rev >= 3) { in b43_calc_nrssi_slope()
664 b43_phy_write(dev, 0x002E, backup[10]); in b43_calc_nrssi_slope()
665 b43_phy_write(dev, 0x002F, backup[11]); in b43_calc_nrssi_slope()
666 b43_phy_write(dev, 0x080F, backup[12]); in b43_calc_nrssi_slope()
667 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); in b43_calc_nrssi_slope()
669 if (phy->rev >= 2) { in b43_calc_nrssi_slope()
670 b43_phy_mask(dev, 0x0812, 0xFFCF); in b43_calc_nrssi_slope()
671 b43_phy_mask(dev, 0x0811, 0xFFCF); in b43_calc_nrssi_slope()
674 b43_radio_write16(dev, 0x007A, backup[0]); in b43_calc_nrssi_slope()
675 b43_radio_write16(dev, 0x0052, backup[1]); in b43_calc_nrssi_slope()
676 b43_radio_write16(dev, 0x0043, backup[2]); in b43_calc_nrssi_slope()
677 b43_write16(dev, 0x03E2, backup[7]); in b43_calc_nrssi_slope()
678 b43_write16(dev, 0x03E6, backup[8]); in b43_calc_nrssi_slope()
679 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]); in b43_calc_nrssi_slope()
680 b43_phy_write(dev, 0x0015, backup[3]); in b43_calc_nrssi_slope()
681 b43_phy_write(dev, 0x005A, backup[4]); in b43_calc_nrssi_slope()
682 b43_phy_write(dev, 0x0059, backup[5]); in b43_calc_nrssi_slope()
683 b43_phy_write(dev, 0x0058, backup[6]); in b43_calc_nrssi_slope()
684 b43_synth_pu_workaround(dev, phy->channel); in b43_calc_nrssi_slope()
685 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002)); in b43_calc_nrssi_slope()
686 b43_set_original_gains(dev); in b43_calc_nrssi_slope()
687 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_calc_nrssi_slope()
688 if (phy->rev >= 3) { in b43_calc_nrssi_slope()
689 b43_phy_write(dev, 0x0801, backup[14]); in b43_calc_nrssi_slope()
690 b43_phy_write(dev, 0x0060, backup[15]); in b43_calc_nrssi_slope()
691 b43_phy_write(dev, 0x0014, backup[16]); in b43_calc_nrssi_slope()
692 b43_phy_write(dev, 0x0478, backup[17]); in b43_calc_nrssi_slope()
694 b43_nrssi_mem_update(dev); in b43_calc_nrssi_slope()
695 b43_calc_nrssi_threshold(dev); in b43_calc_nrssi_slope()
698 static void b43_calc_nrssi_threshold(struct b43_wldev *dev) in b43_calc_nrssi_threshold() argument
700 struct b43_phy *phy = &dev->phy; in b43_calc_nrssi_threshold()
701 struct b43_phy_g *gphy = phy->g; in b43_calc_nrssi_threshold()
706 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_calc_nrssi_threshold()
708 if (!phy->gmode || in b43_calc_nrssi_threshold()
709 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_calc_nrssi_threshold()
710 tmp16 = b43_nrssi_hw_read(dev, 0x20); in b43_calc_nrssi_threshold()
711 if (tmp16 >= 0x20) in b43_calc_nrssi_threshold()
712 tmp16 -= 0x40; in b43_calc_nrssi_threshold()
714 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB); in b43_calc_nrssi_threshold()
716 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED); in b43_calc_nrssi_threshold()
719 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) { in b43_calc_nrssi_threshold()
720 a = 0xE; in b43_calc_nrssi_threshold()
721 b = 0xA; in b43_calc_nrssi_threshold()
722 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) { in b43_calc_nrssi_threshold()
723 a = 0x13; in b43_calc_nrssi_threshold()
724 b = 0x12; in b43_calc_nrssi_threshold()
726 a = 0xE; in b43_calc_nrssi_threshold()
727 b = 0x11; in b43_calc_nrssi_threshold()
730 a = a * (gphy->nrssi[1] - gphy->nrssi[0]); in b43_calc_nrssi_threshold()
731 a += (gphy->nrssi[0] << 6); in b43_calc_nrssi_threshold()
737 a = clamp_val(a, -31, 31); in b43_calc_nrssi_threshold()
739 b = b * (gphy->nrssi[1] - gphy->nrssi[0]); in b43_calc_nrssi_threshold()
740 b += (gphy->nrssi[0] << 6); in b43_calc_nrssi_threshold()
746 b = clamp_val(b, -31, 31); in b43_calc_nrssi_threshold()
748 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; in b43_calc_nrssi_threshold()
749 tmp_u16 |= ((u32) b & 0x0000003F); in b43_calc_nrssi_threshold()
750 tmp_u16 |= (((u32) a & 0x0000003F) << 6); in b43_calc_nrssi_threshold()
751 b43_phy_write(dev, 0x048A, tmp_u16); in b43_calc_nrssi_threshold()
764 B43_WARN_ON(offset & 0xF000); in _stack_save()
765 B43_WARN_ON(id & 0xF0); in _stack_save()
777 B43_WARN_ON(offset & 0xF000); in _stack_restore()
778 B43_WARN_ON(id & 0xF0); in _stack_restore()
779 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) { in _stack_restore()
780 if ((*stackptr & 0x00000FFF) != offset) in _stack_restore()
782 if (((*stackptr & 0x0000F000) >> 12) != id) in _stack_restore()
784 return ((*stackptr & 0xFFFF0000) >> 16); in _stack_restore()
788 return 0; in _stack_restore()
793 _stack_save(stack, &stackidx, 0x1, (offset), \
794 b43_phy_read(dev, (offset))); \
795 } while (0)
798 b43_phy_write(dev, (offset), \
799 _stack_restore(stack, 0x1, \
801 } while (0)
804 _stack_save(stack, &stackidx, 0x2, (offset), \
805 b43_radio_read16(dev, (offset))); \
806 } while (0)
809 b43_radio_write16(dev, (offset), \
810 _stack_restore(stack, 0x2, \
812 } while (0)
815 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
816 b43_ofdmtab_read16(dev, (table), (offset))); \
817 } while (0)
820 b43_ofdmtab_write16(dev, (table), (offset), \
821 _stack_restore(stack, 0x3, \
823 } while (0)
826 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_enable() argument
828 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_enable()
829 struct b43_phy_g *gphy = phy->g; in b43_radio_interference_mitigation_enable()
831 size_t stackidx = 0; in b43_radio_interference_mitigation_enable()
832 u32 *stack = gphy->interfstack; in b43_radio_interference_mitigation_enable()
836 if (phy->rev != 1) { in b43_radio_interference_mitigation_enable()
837 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
838 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000); in b43_radio_interference_mitigation_enable()
841 radio_stacksave(0x0078); in b43_radio_interference_mitigation_enable()
842 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); in b43_radio_interference_mitigation_enable()
848 flipped -= 3; in b43_radio_interference_mitigation_enable()
849 flipped = (bitrev4(flipped) << 1) | 0x0020; in b43_radio_interference_mitigation_enable()
850 b43_radio_write16(dev, 0x0078, flipped); in b43_radio_interference_mitigation_enable()
852 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_enable()
854 phy_stacksave(0x0406); in b43_radio_interference_mitigation_enable()
855 b43_phy_write(dev, 0x0406, 0x7E28); in b43_radio_interference_mitigation_enable()
857 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
858 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); in b43_radio_interference_mitigation_enable()
860 phy_stacksave(0x04A0); in b43_radio_interference_mitigation_enable()
861 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008); in b43_radio_interference_mitigation_enable()
862 phy_stacksave(0x04A1); in b43_radio_interference_mitigation_enable()
863 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
864 phy_stacksave(0x04A2); in b43_radio_interference_mitigation_enable()
865 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204); in b43_radio_interference_mitigation_enable()
866 phy_stacksave(0x04A8); in b43_radio_interference_mitigation_enable()
867 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803); in b43_radio_interference_mitigation_enable()
868 phy_stacksave(0x04AB); in b43_radio_interference_mitigation_enable()
869 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605); in b43_radio_interference_mitigation_enable()
871 phy_stacksave(0x04A7); in b43_radio_interference_mitigation_enable()
872 b43_phy_write(dev, 0x04A7, 0x0002); in b43_radio_interference_mitigation_enable()
873 phy_stacksave(0x04A3); in b43_radio_interference_mitigation_enable()
874 b43_phy_write(dev, 0x04A3, 0x287A); in b43_radio_interference_mitigation_enable()
875 phy_stacksave(0x04A9); in b43_radio_interference_mitigation_enable()
876 b43_phy_write(dev, 0x04A9, 0x2027); in b43_radio_interference_mitigation_enable()
877 phy_stacksave(0x0493); in b43_radio_interference_mitigation_enable()
878 b43_phy_write(dev, 0x0493, 0x32F5); in b43_radio_interference_mitigation_enable()
879 phy_stacksave(0x04AA); in b43_radio_interference_mitigation_enable()
880 b43_phy_write(dev, 0x04AA, 0x2027); in b43_radio_interference_mitigation_enable()
881 phy_stacksave(0x04AC); in b43_radio_interference_mitigation_enable()
882 b43_phy_write(dev, 0x04AC, 0x32F5); in b43_radio_interference_mitigation_enable()
885 if (b43_phy_read(dev, 0x0033) & 0x0800) in b43_radio_interference_mitigation_enable()
888 gphy->aci_enable = true; in b43_radio_interference_mitigation_enable()
892 if (phy->rev < 2) { in b43_radio_interference_mitigation_enable()
893 phy_stacksave(0x0406); in b43_radio_interference_mitigation_enable()
895 phy_stacksave(0x04C0); in b43_radio_interference_mitigation_enable()
896 phy_stacksave(0x04C1); in b43_radio_interference_mitigation_enable()
898 phy_stacksave(0x0033); in b43_radio_interference_mitigation_enable()
899 phy_stacksave(0x04A7); in b43_radio_interference_mitigation_enable()
900 phy_stacksave(0x04A3); in b43_radio_interference_mitigation_enable()
901 phy_stacksave(0x04A9); in b43_radio_interference_mitigation_enable()
902 phy_stacksave(0x04AA); in b43_radio_interference_mitigation_enable()
903 phy_stacksave(0x04AC); in b43_radio_interference_mitigation_enable()
904 phy_stacksave(0x0493); in b43_radio_interference_mitigation_enable()
905 phy_stacksave(0x04A1); in b43_radio_interference_mitigation_enable()
906 phy_stacksave(0x04A0); in b43_radio_interference_mitigation_enable()
907 phy_stacksave(0x04A2); in b43_radio_interference_mitigation_enable()
908 phy_stacksave(0x048A); in b43_radio_interference_mitigation_enable()
909 phy_stacksave(0x04A8); in b43_radio_interference_mitigation_enable()
910 phy_stacksave(0x04AB); in b43_radio_interference_mitigation_enable()
911 if (phy->rev == 2) { in b43_radio_interference_mitigation_enable()
912 phy_stacksave(0x04AD); in b43_radio_interference_mitigation_enable()
913 phy_stacksave(0x04AE); in b43_radio_interference_mitigation_enable()
914 } else if (phy->rev >= 3) { in b43_radio_interference_mitigation_enable()
915 phy_stacksave(0x04AD); in b43_radio_interference_mitigation_enable()
916 phy_stacksave(0x0415); in b43_radio_interference_mitigation_enable()
917 phy_stacksave(0x0416); in b43_radio_interference_mitigation_enable()
918 phy_stacksave(0x0417); in b43_radio_interference_mitigation_enable()
919 ofdmtab_stacksave(0x1A00, 0x2); in b43_radio_interference_mitigation_enable()
920 ofdmtab_stacksave(0x1A00, 0x3); in b43_radio_interference_mitigation_enable()
922 phy_stacksave(0x042B); in b43_radio_interference_mitigation_enable()
923 phy_stacksave(0x048C); in b43_radio_interference_mitigation_enable()
925 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); in b43_radio_interference_mitigation_enable()
926 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002); in b43_radio_interference_mitigation_enable()
928 b43_phy_write(dev, 0x0033, 0x0800); in b43_radio_interference_mitigation_enable()
929 b43_phy_write(dev, 0x04A3, 0x2027); in b43_radio_interference_mitigation_enable()
930 b43_phy_write(dev, 0x04A9, 0x1CA8); in b43_radio_interference_mitigation_enable()
931 b43_phy_write(dev, 0x0493, 0x287A); in b43_radio_interference_mitigation_enable()
932 b43_phy_write(dev, 0x04AA, 0x1CA8); in b43_radio_interference_mitigation_enable()
933 b43_phy_write(dev, 0x04AC, 0x287A); in b43_radio_interference_mitigation_enable()
935 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A); in b43_radio_interference_mitigation_enable()
936 b43_phy_write(dev, 0x04A7, 0x000D); in b43_radio_interference_mitigation_enable()
938 if (phy->rev < 2) { in b43_radio_interference_mitigation_enable()
939 b43_phy_write(dev, 0x0406, 0xFF0D); in b43_radio_interference_mitigation_enable()
940 } else if (phy->rev == 2) { in b43_radio_interference_mitigation_enable()
941 b43_phy_write(dev, 0x04C0, 0xFFFF); in b43_radio_interference_mitigation_enable()
942 b43_phy_write(dev, 0x04C1, 0x00A9); in b43_radio_interference_mitigation_enable()
944 b43_phy_write(dev, 0x04C0, 0x00C1); in b43_radio_interference_mitigation_enable()
945 b43_phy_write(dev, 0x04C1, 0x0059); in b43_radio_interference_mitigation_enable()
948 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800); in b43_radio_interference_mitigation_enable()
949 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015); in b43_radio_interference_mitigation_enable()
950 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
951 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00); in b43_radio_interference_mitigation_enable()
952 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000); in b43_radio_interference_mitigation_enable()
953 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
954 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
955 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005); in b43_radio_interference_mitigation_enable()
956 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010); in b43_radio_interference_mitigation_enable()
957 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006); in b43_radio_interference_mitigation_enable()
958 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800); in b43_radio_interference_mitigation_enable()
959 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500); in b43_radio_interference_mitigation_enable()
960 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B); in b43_radio_interference_mitigation_enable()
962 if (phy->rev >= 3) { in b43_radio_interference_mitigation_enable()
963 b43_phy_mask(dev, 0x048A, 0x7FFF); in b43_radio_interference_mitigation_enable()
964 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
965 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8); in b43_radio_interference_mitigation_enable()
966 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D); in b43_radio_interference_mitigation_enable()
968 b43_phy_set(dev, 0x048A, 0x1000); in b43_radio_interference_mitigation_enable()
969 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000); in b43_radio_interference_mitigation_enable()
970 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); in b43_radio_interference_mitigation_enable()
972 if (phy->rev >= 2) { in b43_radio_interference_mitigation_enable()
973 b43_phy_set(dev, 0x042B, 0x0800); in b43_radio_interference_mitigation_enable()
975 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200); in b43_radio_interference_mitigation_enable()
976 if (phy->rev == 2) { in b43_radio_interference_mitigation_enable()
977 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F); in b43_radio_interference_mitigation_enable()
978 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300); in b43_radio_interference_mitigation_enable()
979 } else if (phy->rev >= 6) { in b43_radio_interference_mitigation_enable()
980 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); in b43_radio_interference_mitigation_enable()
981 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); in b43_radio_interference_mitigation_enable()
982 b43_phy_mask(dev, 0x04AD, 0x00FF); in b43_radio_interference_mitigation_enable()
984 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_enable()
992 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode) in b43_radio_interference_mitigation_disable() argument
994 struct b43_phy *phy = &dev->phy; in b43_radio_interference_mitigation_disable()
995 struct b43_phy_g *gphy = phy->g; in b43_radio_interference_mitigation_disable()
996 u32 *stack = gphy->interfstack; in b43_radio_interference_mitigation_disable()
1000 if (phy->rev != 1) { in b43_radio_interference_mitigation_disable()
1001 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1002 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1005 radio_stackrestore(0x0078); in b43_radio_interference_mitigation_disable()
1006 b43_calc_nrssi_threshold(dev); in b43_radio_interference_mitigation_disable()
1007 phy_stackrestore(0x0406); in b43_radio_interference_mitigation_disable()
1008 b43_phy_mask(dev, 0x042B, ~0x0800); in b43_radio_interference_mitigation_disable()
1009 if (!dev->bad_frames_preempt) { in b43_radio_interference_mitigation_disable()
1010 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11)); in b43_radio_interference_mitigation_disable()
1012 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); in b43_radio_interference_mitigation_disable()
1013 phy_stackrestore(0x04A0); in b43_radio_interference_mitigation_disable()
1014 phy_stackrestore(0x04A1); in b43_radio_interference_mitigation_disable()
1015 phy_stackrestore(0x04A2); in b43_radio_interference_mitigation_disable()
1016 phy_stackrestore(0x04A8); in b43_radio_interference_mitigation_disable()
1017 phy_stackrestore(0x04AB); in b43_radio_interference_mitigation_disable()
1018 phy_stackrestore(0x04A7); in b43_radio_interference_mitigation_disable()
1019 phy_stackrestore(0x04A3); in b43_radio_interference_mitigation_disable()
1020 phy_stackrestore(0x04A9); in b43_radio_interference_mitigation_disable()
1021 phy_stackrestore(0x0493); in b43_radio_interference_mitigation_disable()
1022 phy_stackrestore(0x04AA); in b43_radio_interference_mitigation_disable()
1023 phy_stackrestore(0x04AC); in b43_radio_interference_mitigation_disable()
1026 if (!(b43_phy_read(dev, 0x0033) & 0x0800)) in b43_radio_interference_mitigation_disable()
1029 gphy->aci_enable = false; in b43_radio_interference_mitigation_disable()
1033 phy_stackrestore(0x0033); in b43_radio_interference_mitigation_disable()
1034 phy_stackrestore(0x04A3); in b43_radio_interference_mitigation_disable()
1035 phy_stackrestore(0x04A9); in b43_radio_interference_mitigation_disable()
1036 phy_stackrestore(0x0493); in b43_radio_interference_mitigation_disable()
1037 phy_stackrestore(0x04AA); in b43_radio_interference_mitigation_disable()
1038 phy_stackrestore(0x04AC); in b43_radio_interference_mitigation_disable()
1039 phy_stackrestore(0x04A0); in b43_radio_interference_mitigation_disable()
1040 phy_stackrestore(0x04A7); in b43_radio_interference_mitigation_disable()
1041 if (phy->rev >= 2) { in b43_radio_interference_mitigation_disable()
1042 phy_stackrestore(0x04C0); in b43_radio_interference_mitigation_disable()
1043 phy_stackrestore(0x04C1); in b43_radio_interference_mitigation_disable()
1045 phy_stackrestore(0x0406); in b43_radio_interference_mitigation_disable()
1046 phy_stackrestore(0x04A1); in b43_radio_interference_mitigation_disable()
1047 phy_stackrestore(0x04AB); in b43_radio_interference_mitigation_disable()
1048 phy_stackrestore(0x04A8); in b43_radio_interference_mitigation_disable()
1049 if (phy->rev == 2) { in b43_radio_interference_mitigation_disable()
1050 phy_stackrestore(0x04AD); in b43_radio_interference_mitigation_disable()
1051 phy_stackrestore(0x04AE); in b43_radio_interference_mitigation_disable()
1052 } else if (phy->rev >= 3) { in b43_radio_interference_mitigation_disable()
1053 phy_stackrestore(0x04AD); in b43_radio_interference_mitigation_disable()
1054 phy_stackrestore(0x0415); in b43_radio_interference_mitigation_disable()
1055 phy_stackrestore(0x0416); in b43_radio_interference_mitigation_disable()
1056 phy_stackrestore(0x0417); in b43_radio_interference_mitigation_disable()
1057 ofdmtab_stackrestore(0x1A00, 0x2); in b43_radio_interference_mitigation_disable()
1058 ofdmtab_stackrestore(0x1A00, 0x3); in b43_radio_interference_mitigation_disable()
1060 phy_stackrestore(0x04A2); in b43_radio_interference_mitigation_disable()
1061 phy_stackrestore(0x048A); in b43_radio_interference_mitigation_disable()
1062 phy_stackrestore(0x042B); in b43_radio_interference_mitigation_disable()
1063 phy_stackrestore(0x048C); in b43_radio_interference_mitigation_disable()
1064 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW); in b43_radio_interference_mitigation_disable()
1065 b43_calc_nrssi_slope(dev); in b43_radio_interference_mitigation_disable()
1079 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev) in b43_radio_core_calibration_value() argument
1084 0x02, 0x03, 0x01, 0x0F, in b43_radio_core_calibration_value()
1085 0x06, 0x07, 0x05, 0x0F, in b43_radio_core_calibration_value()
1086 0x0A, 0x0B, 0x09, 0x0F, in b43_radio_core_calibration_value()
1087 0x0E, 0x0F, 0x0D, 0x0F, in b43_radio_core_calibration_value()
1090 reg = b43_radio_read16(dev, 0x60); in b43_radio_core_calibration_value()
1091 index = (reg & 0x001E) >> 1; in b43_radio_core_calibration_value()
1093 ret |= (reg & 0x0001); in b43_radio_core_calibration_value()
1094 ret |= 0x0020; in b43_radio_core_calibration_value()
1099 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1100 static u16 radio2050_rfover_val(struct b43_wldev *dev, in radio2050_rfover_val() argument
1103 struct b43_phy *phy = &dev->phy; in radio2050_rfover_val()
1104 struct b43_phy_g *gphy = phy->g; in radio2050_rfover_val()
1105 struct ssb_sprom *sprom = dev->dev->bus_sprom; in radio2050_rfover_val()
1107 if (!phy->gmode) in radio2050_rfover_val()
1108 return 0; in radio2050_rfover_val()
1111 int max_lb_gain = gphy->max_lb_gain; in radio2050_rfover_val()
1115 if (phy->radio_rev == 8) in radio2050_rfover_val()
1116 max_lb_gain += 0x3E; in radio2050_rfover_val()
1118 max_lb_gain += 0x26; in radio2050_rfover_val()
1119 if (max_lb_gain >= 0x46) { in radio2050_rfover_val()
1120 extlna = 0x3000; in radio2050_rfover_val()
1121 max_lb_gain -= 0x46; in radio2050_rfover_val()
1122 } else if (max_lb_gain >= 0x3A) { in radio2050_rfover_val()
1123 extlna = 0x1000; in radio2050_rfover_val()
1124 max_lb_gain -= 0x3A; in radio2050_rfover_val()
1125 } else if (max_lb_gain >= 0x2E) { in radio2050_rfover_val()
1126 extlna = 0x2000; in radio2050_rfover_val()
1127 max_lb_gain -= 0x2E; in radio2050_rfover_val()
1129 extlna = 0; in radio2050_rfover_val()
1130 max_lb_gain -= 0x10; in radio2050_rfover_val()
1133 for (i = 0; i < 16; i++) { in radio2050_rfover_val()
1134 max_lb_gain -= (i * 6); in radio2050_rfover_val()
1139 if ((phy->rev < 7) || in radio2050_rfover_val()
1140 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { in radio2050_rfover_val()
1142 return 0x1B3; in radio2050_rfover_val()
1146 case LPD(0, 1, 1): in radio2050_rfover_val()
1147 return 0x0F92; in radio2050_rfover_val()
1148 case LPD(0, 0, 1): in radio2050_rfover_val()
1149 case LPD(1, 0, 1): in radio2050_rfover_val()
1150 return (0x0092 | extlna); in radio2050_rfover_val()
1151 case LPD(1, 0, 0): in radio2050_rfover_val()
1152 return (0x0093 | extlna); in radio2050_rfover_val()
1159 return 0x9B3; in radio2050_rfover_val()
1162 extlna |= 0x8000; in radio2050_rfover_val()
1165 case LPD(0, 1, 1): in radio2050_rfover_val()
1166 return 0x8F92; in radio2050_rfover_val()
1167 case LPD(0, 0, 1): in radio2050_rfover_val()
1168 return (0x8092 | extlna); in radio2050_rfover_val()
1169 case LPD(1, 0, 1): in radio2050_rfover_val()
1170 return (0x2092 | extlna); in radio2050_rfover_val()
1171 case LPD(1, 0, 0): in radio2050_rfover_val()
1172 return (0x2093 | extlna); in radio2050_rfover_val()
1179 if ((phy->rev < 7) || in radio2050_rfover_val()
1180 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { in radio2050_rfover_val()
1182 return 0x1B3; in radio2050_rfover_val()
1185 case LPD(0, 1, 1): in radio2050_rfover_val()
1186 return 0x0FB2; in radio2050_rfover_val()
1187 case LPD(0, 0, 1): in radio2050_rfover_val()
1188 return 0x00B2; in radio2050_rfover_val()
1189 case LPD(1, 0, 1): in radio2050_rfover_val()
1190 return 0x30B2; in radio2050_rfover_val()
1191 case LPD(1, 0, 0): in radio2050_rfover_val()
1192 return 0x30B3; in radio2050_rfover_val()
1199 return 0x9B3; in radio2050_rfover_val()
1202 case LPD(0, 1, 1): in radio2050_rfover_val()
1203 return 0x8FB2; in radio2050_rfover_val()
1204 case LPD(0, 0, 1): in radio2050_rfover_val()
1205 return 0x80B2; in radio2050_rfover_val()
1206 case LPD(1, 0, 1): in radio2050_rfover_val()
1207 return 0x20B2; in radio2050_rfover_val()
1208 case LPD(1, 0, 0): in radio2050_rfover_val()
1209 return 0x20B3; in radio2050_rfover_val()
1216 return 0; in radio2050_rfover_val()
1245 static u16 b43_radio_init2050(struct b43_wldev *dev) in b43_radio_init2050() argument
1247 struct b43_phy *phy = &dev->phy; in b43_radio_init2050()
1253 u32 tmp1 = 0, tmp2 = 0; in b43_radio_init2050()
1255 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */ in b43_radio_init2050()
1257 sav.radio_43 = b43_radio_read16(dev, 0x43); in b43_radio_init2050()
1258 sav.radio_51 = b43_radio_read16(dev, 0x51); in b43_radio_init2050()
1259 sav.radio_52 = b43_radio_read16(dev, 0x52); in b43_radio_init2050()
1260 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); in b43_radio_init2050()
1261 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_radio_init2050()
1262 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_radio_init2050()
1263 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_radio_init2050()
1265 if (phy->type == B43_PHYTYPE_B) { in b43_radio_init2050()
1266 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); in b43_radio_init2050()
1267 sav.reg_3EC = b43_read16(dev, 0x3EC); in b43_radio_init2050()
1269 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); in b43_radio_init2050()
1270 b43_write16(dev, 0x3EC, 0x3F3F); in b43_radio_init2050()
1271 } else if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1272 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_radio_init2050()
1273 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_radio_init2050()
1274 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_radio_init2050()
1276 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_radio_init2050()
1277 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); in b43_radio_init2050()
1278 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); in b43_radio_init2050()
1280 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); in b43_radio_init2050()
1281 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); in b43_radio_init2050()
1282 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); in b43_radio_init2050()
1283 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); in b43_radio_init2050()
1285 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_radio_init2050()
1286 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_radio_init2050()
1288 if (phy->rev >= 3) in b43_radio_init2050()
1289 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_radio_init2050()
1291 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_radio_init2050()
1292 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_radio_init2050()
1295 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1296 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1297 LPD(0, 1, 1))); in b43_radio_init2050()
1298 b43_phy_write(dev, B43_PHY_RFOVER, in b43_radio_init2050()
1299 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0)); in b43_radio_init2050()
1301 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); in b43_radio_init2050()
1303 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); in b43_radio_init2050()
1304 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F); in b43_radio_init2050()
1305 sav.reg_3E6 = b43_read16(dev, 0x3E6); in b43_radio_init2050()
1306 sav.reg_3F4 = b43_read16(dev, 0x3F4); in b43_radio_init2050()
1308 if (phy->analog == 0) { in b43_radio_init2050()
1309 b43_write16(dev, 0x03E6, 0x0122); in b43_radio_init2050()
1311 if (phy->analog >= 2) { in b43_radio_init2050()
1312 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); in b43_radio_init2050()
1314 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_radio_init2050()
1315 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); in b43_radio_init2050()
1318 rcc = b43_radio_core_calibration_value(dev); in b43_radio_init2050()
1320 if (phy->type == B43_PHYTYPE_B) in b43_radio_init2050()
1321 b43_radio_write16(dev, 0x78, 0x26); in b43_radio_init2050()
1322 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1323 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1324 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1325 LPD(0, 1, 1))); in b43_radio_init2050()
1327 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); in b43_radio_init2050()
1328 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); in b43_radio_init2050()
1329 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1330 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1331 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1332 LPD(0, 0, 1))); in b43_radio_init2050()
1334 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0); in b43_radio_init2050()
1335 b43_radio_set(dev, 0x51, 0x0004); in b43_radio_init2050()
1336 if (phy->radio_rev == 8) { in b43_radio_init2050()
1337 b43_radio_write16(dev, 0x43, 0x1F); in b43_radio_init2050()
1339 b43_radio_write16(dev, 0x52, 0); in b43_radio_init2050()
1340 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009); in b43_radio_init2050()
1342 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1344 for (i = 0; i < 16; i++) { in b43_radio_init2050()
1345 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); in b43_radio_init2050()
1346 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1347 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1348 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1349 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1350 radio2050_rfover_val(dev, in b43_radio_init2050()
1352 LPD(1, 0, 1))); in b43_radio_init2050()
1354 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1356 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1357 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1358 radio2050_rfover_val(dev, in b43_radio_init2050()
1360 LPD(1, 0, 1))); in b43_radio_init2050()
1362 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1364 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1365 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1366 radio2050_rfover_val(dev, in b43_radio_init2050()
1368 LPD(1, 0, 0))); in b43_radio_init2050()
1370 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1372 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1373 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1374 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1375 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1376 radio2050_rfover_val(dev, in b43_radio_init2050()
1378 LPD(1, 0, 1))); in b43_radio_init2050()
1380 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1384 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1388 for (i = 0; i < 16; i++) { in b43_radio_init2050()
1389 radio78 = (bitrev4(i) << 1) | 0x0020; in b43_radio_init2050()
1390 b43_radio_write16(dev, 0x78, radio78); in b43_radio_init2050()
1392 for (j = 0; j < 16; j++) { in b43_radio_init2050()
1393 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); in b43_radio_init2050()
1394 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_radio_init2050()
1395 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_radio_init2050()
1396 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1397 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1398 radio2050_rfover_val(dev, in b43_radio_init2050()
1400 LPD(1, 0, in b43_radio_init2050()
1403 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1405 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1406 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1407 radio2050_rfover_val(dev, in b43_radio_init2050()
1409 LPD(1, 0, in b43_radio_init2050()
1412 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); in b43_radio_init2050()
1414 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1415 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1416 radio2050_rfover_val(dev, in b43_radio_init2050()
1418 LPD(1, 0, in b43_radio_init2050()
1419 0))); in b43_radio_init2050()
1421 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); in b43_radio_init2050()
1423 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_radio_init2050()
1424 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); in b43_radio_init2050()
1425 if (phy->gmode || phy->rev >= 2) { in b43_radio_init2050()
1426 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_radio_init2050()
1427 radio2050_rfover_val(dev, in b43_radio_init2050()
1429 LPD(1, 0, in b43_radio_init2050()
1432 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); in b43_radio_init2050()
1441 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl); in b43_radio_init2050()
1442 b43_radio_write16(dev, 0x51, sav.radio_51); in b43_radio_init2050()
1443 b43_radio_write16(dev, 0x52, sav.radio_52); in b43_radio_init2050()
1444 b43_radio_write16(dev, 0x43, sav.radio_43); in b43_radio_init2050()
1445 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); in b43_radio_init2050()
1446 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); in b43_radio_init2050()
1447 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); in b43_radio_init2050()
1448 b43_write16(dev, 0x3E6, sav.reg_3E6); in b43_radio_init2050()
1449 if (phy->analog != 0) in b43_radio_init2050()
1450 b43_write16(dev, 0x3F4, sav.reg_3F4); in b43_radio_init2050()
1451 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); in b43_radio_init2050()
1452 b43_synth_pu_workaround(dev, phy->channel); in b43_radio_init2050()
1453 if (phy->type == B43_PHYTYPE_B) { in b43_radio_init2050()
1454 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); in b43_radio_init2050()
1455 b43_write16(dev, 0x3EC, sav.reg_3EC); in b43_radio_init2050()
1456 } else if (phy->gmode) { in b43_radio_init2050()
1457 b43_write16(dev, B43_MMIO_PHY_RADIO, in b43_radio_init2050()
1458 b43_read16(dev, B43_MMIO_PHY_RADIO) in b43_radio_init2050()
1459 & 0x7FFF); in b43_radio_init2050()
1460 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover); in b43_radio_init2050()
1461 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval); in b43_radio_init2050()
1462 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover); in b43_radio_init2050()
1463 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, in b43_radio_init2050()
1465 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0); in b43_radio_init2050()
1466 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl); in b43_radio_init2050()
1468 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask); in b43_radio_init2050()
1469 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl); in b43_radio_init2050()
1480 static void b43_phy_initb5(struct b43_wldev *dev) in b43_phy_initb5() argument
1482 struct b43_phy *phy = &dev->phy; in b43_phy_initb5()
1483 struct b43_phy_g *gphy = phy->g; in b43_phy_initb5()
1487 if (phy->analog == 1) { in b43_phy_initb5()
1488 b43_radio_set(dev, 0x007A, 0x0050); in b43_phy_initb5()
1490 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) && in b43_phy_initb5()
1491 (dev->dev->board_type != SSB_BOARD_BU4306)) { in b43_phy_initb5()
1492 value = 0x2120; in b43_phy_initb5()
1493 for (offset = 0x00A8; offset < 0x00C7; offset++) { in b43_phy_initb5()
1494 b43_phy_write(dev, offset, value); in b43_phy_initb5()
1495 value += 0x202; in b43_phy_initb5()
1498 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700); in b43_phy_initb5()
1499 if (phy->radio_ver == 0x2050) in b43_phy_initb5()
1500 b43_phy_write(dev, 0x0038, 0x0667); in b43_phy_initb5()
1502 if (phy->gmode || phy->rev >= 2) { in b43_phy_initb5()
1503 if (phy->radio_ver == 0x2050) { in b43_phy_initb5()
1504 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb5()
1505 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb5()
1507 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000); in b43_phy_initb5()
1509 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb5()
1510 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb5()
1512 b43_phy_write(dev, 0x001C, 0x186A); in b43_phy_initb5()
1514 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900); in b43_phy_initb5()
1515 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064); in b43_phy_initb5()
1516 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A); in b43_phy_initb5()
1519 if (dev->bad_frames_preempt) { in b43_phy_initb5()
1520 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11)); in b43_phy_initb5()
1523 if (phy->analog == 1) { in b43_phy_initb5()
1524 b43_phy_write(dev, 0x0026, 0xCE00); in b43_phy_initb5()
1525 b43_phy_write(dev, 0x0021, 0x3763); in b43_phy_initb5()
1526 b43_phy_write(dev, 0x0022, 0x1BC3); in b43_phy_initb5()
1527 b43_phy_write(dev, 0x0023, 0x06F9); in b43_phy_initb5()
1528 b43_phy_write(dev, 0x0024, 0x037E); in b43_phy_initb5()
1530 b43_phy_write(dev, 0x0026, 0xCC00); in b43_phy_initb5()
1531 b43_phy_write(dev, 0x0030, 0x00C6); in b43_phy_initb5()
1532 b43_write16(dev, 0x03EC, 0x3F22); in b43_phy_initb5()
1534 if (phy->analog == 1) in b43_phy_initb5()
1535 b43_phy_write(dev, 0x0020, 0x3E1C); in b43_phy_initb5()
1537 b43_phy_write(dev, 0x0020, 0x301C); in b43_phy_initb5()
1539 if (phy->analog == 0) in b43_phy_initb5()
1540 b43_write16(dev, 0x03E4, 0x3000); in b43_phy_initb5()
1542 old_channel = phy->channel; in b43_phy_initb5()
1544 b43_gphy_channel_switch(dev, 7, 0); in b43_phy_initb5()
1546 if (phy->radio_ver != 0x2050) { in b43_phy_initb5()
1547 b43_radio_write16(dev, 0x0075, 0x0080); in b43_phy_initb5()
1548 b43_radio_write16(dev, 0x0079, 0x0081); in b43_phy_initb5()
1551 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1552 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb5()
1554 if (phy->radio_ver == 0x2050) { in b43_phy_initb5()
1555 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb5()
1556 b43_radio_write16(dev, 0x005A, 0x0070); in b43_phy_initb5()
1559 b43_radio_write16(dev, 0x005B, 0x007B); in b43_phy_initb5()
1560 b43_radio_write16(dev, 0x005C, 0x00B0); in b43_phy_initb5()
1562 b43_radio_set(dev, 0x007A, 0x0007); in b43_phy_initb5()
1564 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb5()
1566 b43_phy_write(dev, 0x0014, 0x0080); in b43_phy_initb5()
1567 b43_phy_write(dev, 0x0032, 0x00CA); in b43_phy_initb5()
1568 b43_phy_write(dev, 0x002A, 0x88A3); in b43_phy_initb5()
1570 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb5()
1572 if (phy->radio_ver == 0x2050) in b43_phy_initb5()
1573 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb5()
1575 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004); in b43_phy_initb5()
1578 /* https://bcm-v4.sipsolutions.net/802.11/PHY/Init/B6 */
1579 static void b43_phy_initb6(struct b43_wldev *dev) in b43_phy_initb6() argument
1581 struct b43_phy *phy = &dev->phy; in b43_phy_initb6()
1582 struct b43_phy_g *gphy = phy->g; in b43_phy_initb6()
1586 b43_phy_write(dev, 0x003E, 0x817A); in b43_phy_initb6()
1587 b43_radio_write16(dev, 0x007A, in b43_phy_initb6()
1588 (b43_radio_read16(dev, 0x007A) | 0x0058)); in b43_phy_initb6()
1589 if (phy->radio_rev == 4 || phy->radio_rev == 5) { in b43_phy_initb6()
1590 b43_radio_write16(dev, 0x51, 0x37); in b43_phy_initb6()
1591 b43_radio_write16(dev, 0x52, 0x70); in b43_phy_initb6()
1592 b43_radio_write16(dev, 0x53, 0xB3); in b43_phy_initb6()
1593 b43_radio_write16(dev, 0x54, 0x9B); in b43_phy_initb6()
1594 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1595 b43_radio_write16(dev, 0x5B, 0x88); in b43_phy_initb6()
1596 b43_radio_write16(dev, 0x5D, 0x88); in b43_phy_initb6()
1597 b43_radio_write16(dev, 0x5E, 0x88); in b43_phy_initb6()
1598 b43_radio_write16(dev, 0x7D, 0x88); in b43_phy_initb6()
1599 b43_hf_write(dev, b43_hf_read(dev) in b43_phy_initb6()
1602 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */ in b43_phy_initb6()
1603 if (phy->radio_rev == 8) { in b43_phy_initb6()
1604 b43_radio_write16(dev, 0x51, 0); in b43_phy_initb6()
1605 b43_radio_write16(dev, 0x52, 0x40); in b43_phy_initb6()
1606 b43_radio_write16(dev, 0x53, 0xB7); in b43_phy_initb6()
1607 b43_radio_write16(dev, 0x54, 0x98); in b43_phy_initb6()
1608 b43_radio_write16(dev, 0x5A, 0x88); in b43_phy_initb6()
1609 b43_radio_write16(dev, 0x5B, 0x6B); in b43_phy_initb6()
1610 b43_radio_write16(dev, 0x5C, 0x0F); in b43_phy_initb6()
1611 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) { in b43_phy_initb6()
1612 b43_radio_write16(dev, 0x5D, 0xFA); in b43_phy_initb6()
1613 b43_radio_write16(dev, 0x5E, 0xD8); in b43_phy_initb6()
1615 b43_radio_write16(dev, 0x5D, 0xF5); in b43_phy_initb6()
1616 b43_radio_write16(dev, 0x5E, 0xB8); in b43_phy_initb6()
1618 b43_radio_write16(dev, 0x0073, 0x0003); in b43_phy_initb6()
1619 b43_radio_write16(dev, 0x007D, 0x00A8); in b43_phy_initb6()
1620 b43_radio_write16(dev, 0x007C, 0x0001); in b43_phy_initb6()
1621 b43_radio_write16(dev, 0x007E, 0x0008); in b43_phy_initb6()
1623 val = 0x1E1F; in b43_phy_initb6()
1624 for (offset = 0x0088; offset < 0x0098; offset++) { in b43_phy_initb6()
1625 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1626 val -= 0x0202; in b43_phy_initb6()
1628 val = 0x3E3F; in b43_phy_initb6()
1629 for (offset = 0x0098; offset < 0x00A8; offset++) { in b43_phy_initb6()
1630 b43_phy_write(dev, offset, val); in b43_phy_initb6()
1631 val -= 0x0202; in b43_phy_initb6()
1633 val = 0x2120; in b43_phy_initb6()
1634 for (offset = 0x00A8; offset < 0x00C8; offset++) { in b43_phy_initb6()
1635 b43_phy_write(dev, offset, (val & 0x3F3F)); in b43_phy_initb6()
1636 val += 0x0202; in b43_phy_initb6()
1638 if (phy->type == B43_PHYTYPE_G) { in b43_phy_initb6()
1639 b43_radio_set(dev, 0x007A, 0x0020); in b43_phy_initb6()
1640 b43_radio_set(dev, 0x0051, 0x0004); in b43_phy_initb6()
1641 b43_phy_set(dev, 0x0802, 0x0100); in b43_phy_initb6()
1642 b43_phy_set(dev, 0x042B, 0x2000); in b43_phy_initb6()
1643 b43_phy_write(dev, 0x5B, 0); in b43_phy_initb6()
1644 b43_phy_write(dev, 0x5C, 0); in b43_phy_initb6()
1647 old_channel = phy->channel; in b43_phy_initb6()
1649 b43_gphy_channel_switch(dev, 1, 0); in b43_phy_initb6()
1651 b43_gphy_channel_switch(dev, 13, 0); in b43_phy_initb6()
1653 b43_radio_write16(dev, 0x0050, 0x0020); in b43_phy_initb6()
1654 b43_radio_write16(dev, 0x0050, 0x0023); in b43_phy_initb6()
1656 if (phy->radio_rev < 6 || phy->radio_rev == 8) { in b43_phy_initb6()
1657 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C) in b43_phy_initb6()
1658 | 0x0002)); in b43_phy_initb6()
1659 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1661 if (phy->radio_rev <= 2) { in b43_phy_initb6()
1662 b43_radio_write16(dev, 0x50, 0x20); in b43_phy_initb6()
1663 b43_radio_write16(dev, 0x5A, 0x70); in b43_phy_initb6()
1664 b43_radio_write16(dev, 0x5B, 0x7B); in b43_phy_initb6()
1665 b43_radio_write16(dev, 0x5C, 0xB0); in b43_phy_initb6()
1667 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007); in b43_phy_initb6()
1669 b43_gphy_channel_switch(dev, old_channel, 0); in b43_phy_initb6()
1671 b43_phy_write(dev, 0x0014, 0x0200); in b43_phy_initb6()
1672 if (phy->radio_rev >= 6) in b43_phy_initb6()
1673 b43_phy_write(dev, 0x2A, 0x88C2); in b43_phy_initb6()
1675 b43_phy_write(dev, 0x2A, 0x8AC0); in b43_phy_initb6()
1676 b43_phy_write(dev, 0x0038, 0x0668); in b43_phy_initb6()
1677 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); in b43_phy_initb6()
1678 if (phy->radio_rev == 4 || phy->radio_rev == 5) in b43_phy_initb6()
1679 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003); in b43_phy_initb6()
1680 if (phy->radio_rev <= 2) in b43_phy_initb6()
1681 b43_radio_write16(dev, 0x005D, 0x000D); in b43_phy_initb6()
1683 if (phy->analog == 4) { in b43_phy_initb6()
1684 b43_write16(dev, 0x3E4, 9); in b43_phy_initb6()
1685 b43_phy_mask(dev, 0x61, 0x0FFF); in b43_phy_initb6()
1687 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004); in b43_phy_initb6()
1689 if (phy->type == B43_PHYTYPE_B) in b43_phy_initb6()
1691 else if (phy->type == B43_PHYTYPE_G) in b43_phy_initb6()
1692 b43_write16(dev, 0x03E6, 0x0); in b43_phy_initb6()
1695 static void b43_calc_loopback_gain(struct b43_wldev *dev) in b43_calc_loopback_gain() argument
1697 struct b43_phy *phy = &dev->phy; in b43_calc_loopback_gain()
1698 struct b43_phy_g *gphy = phy->g; in b43_calc_loopback_gain()
1699 u16 backup_phy[16] = { 0 }; in b43_calc_loopback_gain()
1706 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0); in b43_calc_loopback_gain()
1707 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG); in b43_calc_loopback_gain()
1708 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER); in b43_calc_loopback_gain()
1709 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_calc_loopback_gain()
1710 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_loopback_gain()
1711 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); in b43_calc_loopback_gain()
1712 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); in b43_calc_loopback_gain()
1714 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); in b43_calc_loopback_gain()
1715 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); in b43_calc_loopback_gain()
1716 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); in b43_calc_loopback_gain()
1717 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); in b43_calc_loopback_gain()
1718 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); in b43_calc_loopback_gain()
1719 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); in b43_calc_loopback_gain()
1720 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); in b43_calc_loopback_gain()
1721 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); in b43_calc_loopback_gain()
1722 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); in b43_calc_loopback_gain()
1723 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); in b43_calc_loopback_gain()
1724 backup_bband = gphy->bbatt.att; in b43_calc_loopback_gain()
1725 backup_radio[0] = b43_radio_read16(dev, 0x52); in b43_calc_loopback_gain()
1726 backup_radio[1] = b43_radio_read16(dev, 0x43); in b43_calc_loopback_gain()
1727 backup_radio[2] = b43_radio_read16(dev, 0x7A); in b43_calc_loopback_gain()
1729 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF); in b43_calc_loopback_gain()
1730 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); in b43_calc_loopback_gain()
1731 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); in b43_calc_loopback_gain()
1732 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1733 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); in b43_calc_loopback_gain()
1734 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1735 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_loopback_gain()
1736 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); in b43_calc_loopback_gain()
1737 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE); in b43_calc_loopback_gain()
1738 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); in b43_calc_loopback_gain()
1739 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD); in b43_calc_loopback_gain()
1741 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); in b43_calc_loopback_gain()
1742 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); in b43_calc_loopback_gain()
1743 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); in b43_calc_loopback_gain()
1744 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10); in b43_calc_loopback_gain()
1746 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); in b43_calc_loopback_gain()
1747 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); in b43_calc_loopback_gain()
1748 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); in b43_calc_loopback_gain()
1750 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); in b43_calc_loopback_gain()
1751 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_loopback_gain()
1752 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); in b43_calc_loopback_gain()
1753 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); in b43_calc_loopback_gain()
1755 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); in b43_calc_loopback_gain()
1757 if (phy->radio_rev == 8) { in b43_calc_loopback_gain()
1758 b43_radio_write16(dev, 0x43, 0x000F); in b43_calc_loopback_gain()
1760 b43_radio_write16(dev, 0x52, 0); in b43_calc_loopback_gain()
1761 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9); in b43_calc_loopback_gain()
1763 b43_gphy_set_baseband_attenuation(dev, 11); in b43_calc_loopback_gain()
1765 if (phy->rev >= 3) in b43_calc_loopback_gain()
1766 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); in b43_calc_loopback_gain()
1768 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); in b43_calc_loopback_gain()
1769 b43_phy_write(dev, B43_PHY_LO_CTL, 0); in b43_calc_loopback_gain()
1771 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); in b43_calc_loopback_gain()
1772 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); in b43_calc_loopback_gain()
1774 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); in b43_calc_loopback_gain()
1775 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); in b43_calc_loopback_gain()
1777 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) { in b43_calc_loopback_gain()
1778 if (phy->rev >= 7) { in b43_calc_loopback_gain()
1779 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); in b43_calc_loopback_gain()
1780 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); in b43_calc_loopback_gain()
1783 b43_radio_mask(dev, 0x7A, 0x00F7); in b43_calc_loopback_gain()
1785 j = 0; in b43_calc_loopback_gain()
1786 loop_i_max = (phy->radio_rev == 8) ? 15 : 9; in b43_calc_loopback_gain()
1787 for (i = 0; i < loop_i_max; i++) { in b43_calc_loopback_gain()
1788 for (j = 0; j < 16; j++) { in b43_calc_loopback_gain()
1789 b43_radio_write16(dev, 0x43, i); in b43_calc_loopback_gain()
1790 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1791 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1792 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1794 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1802 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); in b43_calc_loopback_gain()
1803 trsw_rx = 0x1B; in b43_calc_loopback_gain()
1804 for (j = j - 8; j < 16; j++) { in b43_calc_loopback_gain()
1805 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); in b43_calc_loopback_gain()
1806 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); in b43_calc_loopback_gain()
1807 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); in b43_calc_loopback_gain()
1809 trsw_rx -= 3; in b43_calc_loopback_gain()
1810 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) in b43_calc_loopback_gain()
1814 trsw_rx = 0x18; in b43_calc_loopback_gain()
1817 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ in b43_calc_loopback_gain()
1818 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); in b43_calc_loopback_gain()
1819 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); in b43_calc_loopback_gain()
1821 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); in b43_calc_loopback_gain()
1822 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); in b43_calc_loopback_gain()
1823 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); in b43_calc_loopback_gain()
1824 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); in b43_calc_loopback_gain()
1825 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); in b43_calc_loopback_gain()
1826 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); in b43_calc_loopback_gain()
1827 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); in b43_calc_loopback_gain()
1828 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); in b43_calc_loopback_gain()
1829 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); in b43_calc_loopback_gain()
1831 b43_gphy_set_baseband_attenuation(dev, backup_bband); in b43_calc_loopback_gain()
1833 b43_radio_write16(dev, 0x52, backup_radio[0]); in b43_calc_loopback_gain()
1834 b43_radio_write16(dev, 0x43, backup_radio[1]); in b43_calc_loopback_gain()
1835 b43_radio_write16(dev, 0x7A, backup_radio[2]); in b43_calc_loopback_gain()
1837 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003); in b43_calc_loopback_gain()
1839 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]); in b43_calc_loopback_gain()
1840 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]); in b43_calc_loopback_gain()
1841 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]); in b43_calc_loopback_gain()
1842 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]); in b43_calc_loopback_gain()
1844 gphy->max_lb_gain = in b43_calc_loopback_gain()
1845 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11; in b43_calc_loopback_gain()
1846 gphy->trsw_rx_gain = trsw_rx * 2; in b43_calc_loopback_gain()
1849 static void b43_hardware_pctl_early_init(struct b43_wldev *dev) in b43_hardware_pctl_early_init() argument
1851 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_early_init()
1853 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_early_init()
1854 b43_phy_write(dev, 0x047A, 0xC111); in b43_hardware_pctl_early_init()
1858 b43_phy_mask(dev, 0x0036, 0xFEFF); in b43_hardware_pctl_early_init()
1859 b43_phy_write(dev, 0x002F, 0x0202); in b43_hardware_pctl_early_init()
1860 b43_phy_set(dev, 0x047C, 0x0002); in b43_hardware_pctl_early_init()
1861 b43_phy_set(dev, 0x047A, 0xF000); in b43_hardware_pctl_early_init()
1862 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { in b43_hardware_pctl_early_init()
1863 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1864 b43_phy_set(dev, 0x005D, 0x8000); in b43_hardware_pctl_early_init()
1865 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1866 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1867 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1869 b43_phy_set(dev, 0x0036, 0x0200); in b43_hardware_pctl_early_init()
1870 b43_phy_set(dev, 0x0036, 0x0400); in b43_hardware_pctl_early_init()
1871 b43_phy_mask(dev, 0x005D, 0x7FFF); in b43_hardware_pctl_early_init()
1872 b43_phy_mask(dev, 0x004F, 0xFFFE); in b43_hardware_pctl_early_init()
1873 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); in b43_hardware_pctl_early_init()
1874 b43_phy_write(dev, 0x002E, 0xC07F); in b43_hardware_pctl_early_init()
1875 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); in b43_hardware_pctl_early_init()
1879 /* Hardware power control for G-PHY */
1880 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev) in b43_hardware_pctl_init_gphy() argument
1882 struct b43_phy *phy = &dev->phy; in b43_hardware_pctl_init_gphy()
1883 struct b43_phy_g *gphy = phy->g; in b43_hardware_pctl_init_gphy()
1885 if (!b43_has_hardware_pctl(dev)) { in b43_hardware_pctl_init_gphy()
1887 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1891 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1892 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); in b43_hardware_pctl_init_gphy()
1893 b43_gphy_tssi_power_lt_init(dev); in b43_hardware_pctl_init_gphy()
1894 b43_gphy_gain_lt_init(dev); in b43_hardware_pctl_init_gphy()
1895 b43_phy_mask(dev, 0x0060, 0xFFBF); in b43_hardware_pctl_init_gphy()
1896 b43_phy_write(dev, 0x0014, 0x0000); in b43_hardware_pctl_init_gphy()
1898 B43_WARN_ON(phy->rev < 6); in b43_hardware_pctl_init_gphy()
1899 b43_phy_set(dev, 0x0478, 0x0800); in b43_hardware_pctl_init_gphy()
1900 b43_phy_mask(dev, 0x0478, 0xFEFF); in b43_hardware_pctl_init_gphy()
1901 b43_phy_mask(dev, 0x0801, 0xFFBF); in b43_hardware_pctl_init_gphy()
1903 b43_gphy_dc_lt_init(dev, 1); in b43_hardware_pctl_init_gphy()
1906 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL); in b43_hardware_pctl_init_gphy()
1910 static void b43_phy_init_pctl(struct b43_wldev *dev) in b43_phy_init_pctl() argument
1912 struct b43_phy *phy = &dev->phy; in b43_phy_init_pctl()
1913 struct b43_phy_g *gphy = phy->g; in b43_phy_init_pctl()
1916 u8 old_tx_control = 0; in b43_phy_init_pctl()
1918 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_phy_init_pctl()
1920 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && in b43_phy_init_pctl()
1921 (dev->dev->board_type == SSB_BOARD_BU4306)) in b43_phy_init_pctl()
1924 b43_phy_write(dev, 0x0028, 0x8018); in b43_phy_init_pctl()
1927 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0) in b43_phy_init_pctl()
1928 & 0xFFDF); in b43_phy_init_pctl()
1930 if (!phy->gmode) in b43_phy_init_pctl()
1932 b43_hardware_pctl_early_init(dev); in b43_phy_init_pctl()
1933 if (gphy->cur_idle_tssi == 0) { in b43_phy_init_pctl()
1934 if (phy->radio_ver == 0x2050 && phy->analog == 0) { in b43_phy_init_pctl()
1935 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084); in b43_phy_init_pctl()
1940 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt)); in b43_phy_init_pctl()
1941 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt)); in b43_phy_init_pctl()
1942 old_tx_control = gphy->tx_control; in b43_phy_init_pctl()
1945 if (phy->radio_rev == 8) { in b43_phy_init_pctl()
1952 b43_set_txpower_g(dev, &bbatt, &rfatt, 0); in b43_phy_init_pctl()
1954 b43_dummy_transmission(dev, false, true); in b43_phy_init_pctl()
1955 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI); in b43_phy_init_pctl()
1957 /* Current-Idle-TSSI sanity check. */ in b43_phy_init_pctl()
1958 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) { in b43_phy_init_pctl()
1959 b43dbg(dev->wl, in b43_phy_init_pctl()
1960 "!WARNING! Idle-TSSI phy->cur_idle_tssi " in b43_phy_init_pctl()
1962 "adjustment.\n", gphy->cur_idle_tssi, in b43_phy_init_pctl()
1963 gphy->tgt_idle_tssi); in b43_phy_init_pctl()
1964 gphy->cur_idle_tssi = 0; in b43_phy_init_pctl()
1967 if (phy->radio_ver == 0x2050 && phy->analog == 0) { in b43_phy_init_pctl()
1968 b43_radio_mask(dev, 0x0076, 0xFF7B); in b43_phy_init_pctl()
1970 b43_set_txpower_g(dev, &old_bbatt, in b43_phy_init_pctl()
1974 b43_hardware_pctl_init_gphy(dev); in b43_phy_init_pctl()
1975 b43_shm_clear_tssi(dev); in b43_phy_init_pctl()
1978 static void b43_phy_inita(struct b43_wldev *dev) in b43_phy_inita() argument
1980 struct b43_phy *phy = &dev->phy; in b43_phy_inita()
1984 if (phy->rev >= 6) { in b43_phy_inita()
1985 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) in b43_phy_inita()
1986 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); in b43_phy_inita()
1988 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); in b43_phy_inita()
1991 b43_wa_all(dev); in b43_phy_inita()
1993 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_phy_inita()
1994 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); in b43_phy_inita()
1997 static void b43_phy_initg(struct b43_wldev *dev) in b43_phy_initg() argument
1999 struct b43_phy *phy = &dev->phy; in b43_phy_initg()
2000 struct b43_phy_g *gphy = phy->g; in b43_phy_initg()
2003 if (phy->rev == 1) in b43_phy_initg()
2004 b43_phy_initb5(dev); in b43_phy_initg()
2006 b43_phy_initb6(dev); in b43_phy_initg()
2008 if (phy->rev >= 2 || phy->gmode) in b43_phy_initg()
2009 b43_phy_inita(dev); in b43_phy_initg()
2011 if (phy->rev >= 2) { in b43_phy_initg()
2012 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0); in b43_phy_initg()
2013 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0); in b43_phy_initg()
2015 if (phy->rev == 2) { in b43_phy_initg()
2016 b43_phy_write(dev, B43_PHY_RFOVER, 0); in b43_phy_initg()
2017 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2019 if (phy->rev > 5) { in b43_phy_initg()
2020 b43_phy_write(dev, B43_PHY_RFOVER, 0x400); in b43_phy_initg()
2021 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); in b43_phy_initg()
2023 if (phy->gmode || phy->rev >= 2) { in b43_phy_initg()
2024 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM); in b43_phy_initg()
2027 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); in b43_phy_initg()
2028 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); in b43_phy_initg()
2031 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); in b43_phy_initg()
2034 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2) in b43_phy_initg()
2035 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); in b43_phy_initg()
2036 if (phy->radio_rev == 8) { in b43_phy_initg()
2037 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80); in b43_phy_initg()
2038 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); in b43_phy_initg()
2041 b43_calc_loopback_gain(dev); in b43_phy_initg()
2043 if (phy->radio_rev != 8) { in b43_phy_initg()
2044 if (gphy->initval == 0xFFFF) in b43_phy_initg()
2045 gphy->initval = b43_radio_init2050(dev); in b43_phy_initg()
2047 b43_radio_write16(dev, 0x0078, gphy->initval); in b43_phy_initg()
2049 b43_lo_g_init(dev); in b43_phy_initg()
2051 b43_radio_write16(dev, 0x52, in b43_phy_initg()
2052 (b43_radio_read16(dev, 0x52) & 0xFF00) in b43_phy_initg()
2053 | gphy->lo_control->tx_bias | gphy-> in b43_phy_initg()
2054 lo_control->tx_magn); in b43_phy_initg()
2056 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias); in b43_phy_initg()
2058 if (phy->rev >= 6) { in b43_phy_initg()
2059 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); in b43_phy_initg()
2061 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_phy_initg()
2062 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); in b43_phy_initg()
2064 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); in b43_phy_initg()
2065 if (phy->rev < 2) in b43_phy_initg()
2066 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); in b43_phy_initg()
2068 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); in b43_phy_initg()
2069 if (phy->gmode || phy->rev >= 2) { in b43_phy_initg()
2070 b43_lo_g_adjust(dev); in b43_phy_initg()
2071 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); in b43_phy_initg()
2074 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { in b43_phy_initg()
2076 * the value 0x7FFFFFFF here. I think that is some weird in b43_phy_initg()
2079 * entries to -32 (see the clamp_val() in nrssi_hw_update()) in b43_phy_initg()
2081 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? in b43_phy_initg()
2082 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2083 } else if (phy->gmode || phy->rev >= 2) { in b43_phy_initg()
2084 if (gphy->nrssi[0] == -1000) { in b43_phy_initg()
2085 B43_WARN_ON(gphy->nrssi[1] != -1000); in b43_phy_initg()
2086 b43_calc_nrssi_slope(dev); in b43_phy_initg()
2088 b43_calc_nrssi_threshold(dev); in b43_phy_initg()
2090 if (phy->radio_rev == 8) in b43_phy_initg()
2091 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230); in b43_phy_initg()
2092 b43_phy_init_pctl(dev); in b43_phy_initg()
2093 /* FIXME: The spec says in the following if, the 0 should be replaced in b43_phy_initg()
2096 if ((dev->dev->chip_id == 0x4306 in b43_phy_initg()
2097 && dev->dev->chip_pkg == 2) || 0) { in b43_phy_initg()
2098 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); in b43_phy_initg()
2099 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); in b43_phy_initg()
2103 void b43_gphy_channel_switch(struct b43_wldev *dev, in b43_gphy_channel_switch() argument
2108 b43_synth_pu_workaround(dev, channel); in b43_gphy_channel_switch()
2110 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); in b43_gphy_channel_switch()
2113 if (dev->dev->bus_sprom->country_code == in b43_gphy_channel_switch()
2115 b43_hf_write(dev, in b43_gphy_channel_switch()
2116 b43_hf_read(dev) & ~B43_HF_ACPR); in b43_gphy_channel_switch()
2118 b43_hf_write(dev, in b43_gphy_channel_switch()
2119 b43_hf_read(dev) | B43_HF_ACPR); in b43_gphy_channel_switch()
2120 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2121 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2124 b43_write16(dev, B43_MMIO_CHANNEL_EXT, in b43_gphy_channel_switch()
2125 b43_read16(dev, B43_MMIO_CHANNEL_EXT) in b43_gphy_channel_switch()
2126 & 0xF7BF); in b43_gphy_channel_switch()
2130 static void default_baseband_attenuation(struct b43_wldev *dev, in default_baseband_attenuation() argument
2133 struct b43_phy *phy = &dev->phy; in default_baseband_attenuation()
2135 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6) in default_baseband_attenuation()
2136 bb->att = 0; in default_baseband_attenuation()
2138 bb->att = 2; in default_baseband_attenuation()
2141 static void default_radio_attenuation(struct b43_wldev *dev, in default_radio_attenuation() argument
2144 struct b43_bus_dev *bdev = dev->dev; in default_radio_attenuation()
2145 struct b43_phy *phy = &dev->phy; in default_radio_attenuation()
2147 rf->with_padmix = false; in default_radio_attenuation()
2149 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && in default_radio_attenuation()
2150 dev->dev->board_type == SSB_BOARD_BCM4309G) { in default_radio_attenuation()
2151 if (dev->dev->board_rev < 0x43) { in default_radio_attenuation()
2152 rf->att = 2; in default_radio_attenuation()
2154 } else if (dev->dev->board_rev < 0x51) { in default_radio_attenuation()
2155 rf->att = 3; in default_radio_attenuation()
2160 switch (phy->radio_ver) { in default_radio_attenuation()
2161 case 0x2053: in default_radio_attenuation()
2162 switch (phy->radio_rev) { in default_radio_attenuation()
2164 rf->att = 6; in default_radio_attenuation()
2168 case 0x2050: in default_radio_attenuation()
2169 switch (phy->radio_rev) { in default_radio_attenuation()
2170 case 0: in default_radio_attenuation()
2171 rf->att = 5; in default_radio_attenuation()
2174 if (phy->type == B43_PHYTYPE_G) { in default_radio_attenuation()
2175 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM in default_radio_attenuation()
2176 && bdev->board_type == SSB_BOARD_BCM4309G in default_radio_attenuation()
2177 && bdev->board_rev >= 30) in default_radio_attenuation()
2178 rf->att = 3; in default_radio_attenuation()
2179 else if (bdev->board_vendor == in default_radio_attenuation()
2181 && bdev->board_type == in default_radio_attenuation()
2183 rf->att = 3; in default_radio_attenuation()
2185 rf->att = 1; in default_radio_attenuation()
2187 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM in default_radio_attenuation()
2188 && bdev->board_type == SSB_BOARD_BCM4309G in default_radio_attenuation()
2189 && bdev->board_rev >= 30) in default_radio_attenuation()
2190 rf->att = 7; in default_radio_attenuation()
2192 rf->att = 6; in default_radio_attenuation()
2196 if (phy->type == B43_PHYTYPE_G) { in default_radio_attenuation()
2197 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM in default_radio_attenuation()
2198 && bdev->board_type == SSB_BOARD_BCM4309G in default_radio_attenuation()
2199 && bdev->board_rev >= 30) in default_radio_attenuation()
2200 rf->att = 3; in default_radio_attenuation()
2201 else if (bdev->board_vendor == in default_radio_attenuation()
2203 && bdev->board_type == in default_radio_attenuation()
2205 rf->att = 5; in default_radio_attenuation()
2206 else if (bdev->chip_id == 0x4320) in default_radio_attenuation()
2207 rf->att = 4; in default_radio_attenuation()
2209 rf->att = 3; in default_radio_attenuation()
2211 rf->att = 6; in default_radio_attenuation()
2214 rf->att = 5; in default_radio_attenuation()
2218 rf->att = 1; in default_radio_attenuation()
2222 rf->att = 5; in default_radio_attenuation()
2225 rf->att = 0xA; in default_radio_attenuation()
2226 rf->with_padmix = true; in default_radio_attenuation()
2230 rf->att = 5; in default_radio_attenuation()
2234 rf->att = 5; in default_radio_attenuation()
2237 static u16 default_tx_control(struct b43_wldev *dev) in default_tx_control() argument
2239 struct b43_phy *phy = &dev->phy; in default_tx_control()
2241 if (phy->radio_ver != 0x2050) in default_tx_control()
2242 return 0; in default_tx_control()
2243 if (phy->radio_rev == 1) in default_tx_control()
2245 if (phy->radio_rev < 6) in default_tx_control()
2247 if (phy->radio_rev == 8) in default_tx_control()
2249 return 0; in default_tx_control()
2252 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel) in b43_gphy_aci_detect() argument
2254 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_detect()
2255 struct b43_phy_g *gphy = phy->g; in b43_gphy_aci_detect()
2256 u8 ret = 0; in b43_gphy_aci_detect()
2258 int i, j = 0; in b43_gphy_aci_detect()
2260 saved = b43_phy_read(dev, 0x0403); in b43_gphy_aci_detect()
2261 b43_switch_channel(dev, channel); in b43_gphy_aci_detect()
2262 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5); in b43_gphy_aci_detect()
2263 if (gphy->aci_hw_rssi) in b43_gphy_aci_detect()
2264 rssi = b43_phy_read(dev, 0x048A) & 0x3F; in b43_gphy_aci_detect()
2266 rssi = saved & 0x3F; in b43_gphy_aci_detect()
2269 rssi -= 64; in b43_gphy_aci_detect()
2270 for (i = 0; i < 100; i++) { in b43_gphy_aci_detect()
2271 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F; in b43_gphy_aci_detect()
2273 temp -= 64; in b43_gphy_aci_detect()
2279 b43_phy_write(dev, 0x0403, saved); in b43_gphy_aci_detect()
2284 static u8 b43_gphy_aci_scan(struct b43_wldev *dev) in b43_gphy_aci_scan() argument
2286 struct b43_phy *phy = &dev->phy; in b43_gphy_aci_scan()
2287 u8 ret[13] = { 0 }; in b43_gphy_aci_scan()
2288 unsigned int channel = phy->channel; in b43_gphy_aci_scan()
2291 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0))) in b43_gphy_aci_scan()
2292 return 0; in b43_gphy_aci_scan()
2294 b43_phy_lock(dev); in b43_gphy_aci_scan()
2295 b43_radio_lock(dev); in b43_gphy_aci_scan()
2296 b43_phy_mask(dev, 0x0802, 0xFFFC); in b43_gphy_aci_scan()
2297 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); in b43_gphy_aci_scan()
2298 b43_set_all_gains(dev, 3, 8, 1); in b43_gphy_aci_scan()
2300 start = (channel > 5) ? channel - 5 : 1; in b43_gphy_aci_scan()
2304 if (abs(channel - i) > 2) in b43_gphy_aci_scan()
2305 ret[i - 1] = b43_gphy_aci_detect(dev, i); in b43_gphy_aci_scan()
2307 b43_switch_channel(dev, channel); in b43_gphy_aci_scan()
2308 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003); in b43_gphy_aci_scan()
2309 b43_phy_mask(dev, 0x0403, 0xFFF8); in b43_gphy_aci_scan()
2310 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); in b43_gphy_aci_scan()
2311 b43_set_original_gains(dev); in b43_gphy_aci_scan()
2312 for (i = 0; i < 13; i++) { in b43_gphy_aci_scan()
2319 b43_radio_unlock(dev); in b43_gphy_aci_scan()
2320 b43_phy_unlock(dev); in b43_gphy_aci_scan()
2322 return ret[channel - 1]; in b43_gphy_aci_scan()
2327 if (num < 0) in b43_tssi2dbm_ad()
2337 s8 i = 0; in b43_tssi2dbm_entry()
2343 return -EINVAL; in b43_tssi2dbm_entry()
2344 q = b43_tssi2dbm_ad(f * 4096 - in b43_tssi2dbm_entry()
2346 delta = abs(q - f); in b43_tssi2dbm_entry()
2350 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128); in b43_tssi2dbm_entry()
2351 return 0; in b43_tssi2dbm_entry()
2354 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, in b43_generate_dyn_tssi2dbm_tab() argument
2363 b43err(dev->wl, "Could not allocate memory " in b43_generate_dyn_tssi2dbm_tab()
2367 for (i = 0; i < 64; i++) { in b43_generate_dyn_tssi2dbm_tab()
2370 b43err(dev->wl, "Could not generate " in b43_generate_dyn_tssi2dbm_tab()
2380 /* Initialise the TSSI->dBm lookup table */
2381 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev) in b43_gphy_init_tssi2dbm_table() argument
2383 struct b43_phy *phy = &dev->phy; in b43_gphy_init_tssi2dbm_table()
2384 struct b43_phy_g *gphy = phy->g; in b43_gphy_init_tssi2dbm_table()
2387 pab0 = (s16) (dev->dev->bus_sprom->pa0b0); in b43_gphy_init_tssi2dbm_table()
2388 pab1 = (s16) (dev->dev->bus_sprom->pa0b1); in b43_gphy_init_tssi2dbm_table()
2389 pab2 = (s16) (dev->dev->bus_sprom->pa0b2); in b43_gphy_init_tssi2dbm_table()
2391 B43_WARN_ON((dev->dev->chip_id == 0x4301) && in b43_gphy_init_tssi2dbm_table()
2392 (phy->radio_ver != 0x2050)); /* Not supported anymore */ in b43_gphy_init_tssi2dbm_table()
2394 gphy->dyn_tssi_tbl = false; in b43_gphy_init_tssi2dbm_table()
2396 if (pab0 != 0 && pab1 != 0 && pab2 != 0 && in b43_gphy_init_tssi2dbm_table()
2397 pab0 != -1 && pab1 != -1 && pab2 != -1) { in b43_gphy_init_tssi2dbm_table()
2399 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 && in b43_gphy_init_tssi2dbm_table()
2400 (s8) dev->dev->bus_sprom->itssi_bg != -1) { in b43_gphy_init_tssi2dbm_table()
2401 gphy->tgt_idle_tssi = in b43_gphy_init_tssi2dbm_table()
2402 (s8) (dev->dev->bus_sprom->itssi_bg); in b43_gphy_init_tssi2dbm_table()
2404 gphy->tgt_idle_tssi = 62; in b43_gphy_init_tssi2dbm_table()
2405 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, in b43_gphy_init_tssi2dbm_table()
2407 if (!gphy->tssi2dbm) in b43_gphy_init_tssi2dbm_table()
2408 return -ENOMEM; in b43_gphy_init_tssi2dbm_table()
2409 gphy->dyn_tssi_tbl = true; in b43_gphy_init_tssi2dbm_table()
2412 gphy->tgt_idle_tssi = 52; in b43_gphy_init_tssi2dbm_table()
2413 gphy->tssi2dbm = b43_tssi2dbm_g_table; in b43_gphy_init_tssi2dbm_table()
2416 return 0; in b43_gphy_init_tssi2dbm_table()
2419 static int b43_gphy_op_allocate(struct b43_wldev *dev) in b43_gphy_op_allocate() argument
2427 err = -ENOMEM; in b43_gphy_op_allocate()
2430 dev->phy.g = gphy; in b43_gphy_op_allocate()
2434 err = -ENOMEM; in b43_gphy_op_allocate()
2437 gphy->lo_control = lo; in b43_gphy_op_allocate()
2439 err = b43_gphy_init_tssi2dbm_table(dev); in b43_gphy_op_allocate()
2443 return 0; in b43_gphy_op_allocate()
2453 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev) in b43_gphy_op_prepare_structs() argument
2455 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_structs()
2456 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_prepare_structs()
2464 tssi2dbm = gphy->tssi2dbm; in b43_gphy_op_prepare_structs()
2465 tgt_idle_tssi = gphy->tgt_idle_tssi; in b43_gphy_op_prepare_structs()
2467 lo = gphy->lo_control; in b43_gphy_op_prepare_structs()
2470 memset(gphy, 0, sizeof(*gphy)); in b43_gphy_op_prepare_structs()
2473 gphy->tssi2dbm = tssi2dbm; in b43_gphy_op_prepare_structs()
2474 gphy->tgt_idle_tssi = tgt_idle_tssi; in b43_gphy_op_prepare_structs()
2475 gphy->lo_control = lo; in b43_gphy_op_prepare_structs()
2477 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig)); in b43_gphy_op_prepare_structs()
2480 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++) in b43_gphy_op_prepare_structs()
2481 gphy->nrssi[i] = -1000; in b43_gphy_op_prepare_structs()
2482 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++) in b43_gphy_op_prepare_structs()
2483 gphy->nrssi_lt[i] = i; in b43_gphy_op_prepare_structs()
2485 gphy->lofcal = 0xFFFF; in b43_gphy_op_prepare_structs()
2486 gphy->initval = 0xFFFF; in b43_gphy_op_prepare_structs()
2488 gphy->interfmode = B43_INTERFMODE_NONE; in b43_gphy_op_prepare_structs()
2490 /* OFDM-table address caching. */ in b43_gphy_op_prepare_structs()
2491 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; in b43_gphy_op_prepare_structs()
2493 gphy->average_tssi = 0xFF; in b43_gphy_op_prepare_structs()
2496 lo->tx_bias = 0xFF; in b43_gphy_op_prepare_structs()
2497 INIT_LIST_HEAD(&lo->calib_list); in b43_gphy_op_prepare_structs()
2500 static void b43_gphy_op_free(struct b43_wldev *dev) in b43_gphy_op_free() argument
2502 struct b43_phy *phy = &dev->phy; in b43_gphy_op_free()
2503 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_free()
2505 kfree(gphy->lo_control); in b43_gphy_op_free()
2507 if (gphy->dyn_tssi_tbl) in b43_gphy_op_free()
2508 kfree(gphy->tssi2dbm); in b43_gphy_op_free()
2509 gphy->dyn_tssi_tbl = false; in b43_gphy_op_free()
2510 gphy->tssi2dbm = NULL; in b43_gphy_op_free()
2513 dev->phy.g = NULL; in b43_gphy_op_free()
2516 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev) in b43_gphy_op_prepare_hardware() argument
2518 struct b43_phy *phy = &dev->phy; in b43_gphy_op_prepare_hardware()
2519 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_prepare_hardware()
2520 struct b43_txpower_lo_control *lo = gphy->lo_control; in b43_gphy_op_prepare_hardware()
2522 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_gphy_op_prepare_hardware()
2524 default_baseband_attenuation(dev, &gphy->bbatt); in b43_gphy_op_prepare_hardware()
2525 default_radio_attenuation(dev, &gphy->rfatt); in b43_gphy_op_prepare_hardware()
2526 gphy->tx_control = (default_tx_control(dev) << 4); in b43_gphy_op_prepare_hardware()
2527 generate_rfatt_list(dev, &lo->rfatt_list); in b43_gphy_op_prepare_hardware()
2528 generate_bbatt_list(dev, &lo->bbatt_list); in b43_gphy_op_prepare_hardware()
2531 b43_read32(dev, B43_MMIO_MACCTL); in b43_gphy_op_prepare_hardware()
2533 if (phy->rev == 1) { in b43_gphy_op_prepare_hardware()
2536 phy->gmode = false; in b43_gphy_op_prepare_hardware()
2537 b43_wireless_core_reset(dev, 0); in b43_gphy_op_prepare_hardware()
2538 b43_phy_initg(dev); in b43_gphy_op_prepare_hardware()
2539 phy->gmode = true; in b43_gphy_op_prepare_hardware()
2540 b43_wireless_core_reset(dev, 1); in b43_gphy_op_prepare_hardware()
2543 return 0; in b43_gphy_op_prepare_hardware()
2546 static int b43_gphy_op_init(struct b43_wldev *dev) in b43_gphy_op_init() argument
2548 b43_phy_initg(dev); in b43_gphy_op_init()
2550 return 0; in b43_gphy_op_init()
2553 static void b43_gphy_op_exit(struct b43_wldev *dev) in b43_gphy_op_exit() argument
2555 b43_lo_g_cleanup(dev); in b43_gphy_op_exit()
2558 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_read() argument
2560 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_read()
2561 return b43_read16(dev, B43_MMIO_PHY_DATA); in b43_gphy_op_read()
2564 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_write() argument
2566 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); in b43_gphy_op_write()
2567 b43_write16(dev, B43_MMIO_PHY_DATA, value); in b43_gphy_op_write()
2570 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) in b43_gphy_op_radio_read() argument
2572 /* Register 1 is a 32-bit register. */ in b43_gphy_op_radio_read()
2574 /* G-PHY needs 0x80 for read access. */ in b43_gphy_op_radio_read()
2575 reg |= 0x80; in b43_gphy_op_radio_read()
2577 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_read()
2578 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); in b43_gphy_op_radio_read()
2581 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) in b43_gphy_op_radio_write() argument
2583 /* Register 1 is a 32-bit register. */ in b43_gphy_op_radio_write()
2586 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); in b43_gphy_op_radio_write()
2587 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); in b43_gphy_op_radio_write()
2590 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev) in b43_gphy_op_supports_hwpctl() argument
2592 return (dev->phy.rev >= 6); in b43_gphy_op_supports_hwpctl()
2595 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev, in b43_gphy_op_software_rfkill() argument
2598 struct b43_phy *phy = &dev->phy; in b43_gphy_op_software_rfkill()
2599 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_software_rfkill()
2606 if (phy->radio_on) in b43_gphy_op_software_rfkill()
2609 b43_phy_write(dev, 0x0015, 0x8000); in b43_gphy_op_software_rfkill()
2610 b43_phy_write(dev, 0x0015, 0xCC00); in b43_gphy_op_software_rfkill()
2611 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000)); in b43_gphy_op_software_rfkill()
2612 if (gphy->radio_off_context.valid) { in b43_gphy_op_software_rfkill()
2614 b43_phy_write(dev, B43_PHY_RFOVER, in b43_gphy_op_software_rfkill()
2615 gphy->radio_off_context.rfover); in b43_gphy_op_software_rfkill()
2616 b43_phy_write(dev, B43_PHY_RFOVERVAL, in b43_gphy_op_software_rfkill()
2617 gphy->radio_off_context.rfoverval); in b43_gphy_op_software_rfkill()
2618 gphy->radio_off_context.valid = false; in b43_gphy_op_software_rfkill()
2620 channel = phy->channel; in b43_gphy_op_software_rfkill()
2621 b43_gphy_channel_switch(dev, 6, 1); in b43_gphy_op_software_rfkill()
2622 b43_gphy_channel_switch(dev, channel, 0); in b43_gphy_op_software_rfkill()
2627 rfover = b43_phy_read(dev, B43_PHY_RFOVER); in b43_gphy_op_software_rfkill()
2628 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); in b43_gphy_op_software_rfkill()
2629 gphy->radio_off_context.rfover = rfover; in b43_gphy_op_software_rfkill()
2630 gphy->radio_off_context.rfoverval = rfoverval; in b43_gphy_op_software_rfkill()
2631 gphy->radio_off_context.valid = true; in b43_gphy_op_software_rfkill()
2632 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); in b43_gphy_op_software_rfkill()
2633 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); in b43_gphy_op_software_rfkill()
2637 static int b43_gphy_op_switch_channel(struct b43_wldev *dev, in b43_gphy_op_switch_channel() argument
2641 return -EINVAL; in b43_gphy_op_switch_channel()
2642 b43_gphy_channel_switch(dev, new_channel, 0); in b43_gphy_op_switch_channel()
2644 return 0; in b43_gphy_op_switch_channel()
2647 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev) in b43_gphy_op_get_default_chan() argument
2652 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) in b43_gphy_op_set_rx_antenna() argument
2654 struct b43_phy *phy = &dev->phy; in b43_gphy_op_set_rx_antenna()
2656 int autodiv = 0; in b43_gphy_op_set_rx_antenna()
2661 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2663 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, in b43_gphy_op_set_rx_antenna()
2668 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); in b43_gphy_op_set_rx_antenna()
2673 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); in b43_gphy_op_set_rx_antenna()
2676 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT); in b43_gphy_op_set_rx_antenna()
2681 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp); in b43_gphy_op_set_rx_antenna()
2684 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV); in b43_gphy_op_set_rx_antenna()
2686 b43_phy_mask(dev, B43_PHY_ANTWRSETT, in b43_gphy_op_set_rx_antenna()
2690 if (phy->rev >= 2) { in b43_gphy_op_set_rx_antenna()
2691 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10); in b43_gphy_op_set_rx_antenna()
2692 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15); in b43_gphy_op_set_rx_antenna()
2694 if (phy->rev == 2) in b43_gphy_op_set_rx_antenna()
2695 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); in b43_gphy_op_set_rx_antenna()
2697 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); in b43_gphy_op_set_rx_antenna()
2699 if (phy->rev >= 6) in b43_gphy_op_set_rx_antenna()
2700 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC); in b43_gphy_op_set_rx_antenna()
2702 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); in b43_gphy_op_set_rx_antenna()
2705 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev, in b43_gphy_op_interf_mitigation() argument
2708 struct b43_phy *phy = &dev->phy; in b43_gphy_op_interf_mitigation()
2709 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_interf_mitigation()
2712 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_gphy_op_interf_mitigation()
2713 if ((phy->rev == 0) || (!phy->gmode)) in b43_gphy_op_interf_mitigation()
2714 return -ENODEV; in b43_gphy_op_interf_mitigation()
2716 gphy->aci_wlan_automatic = false; in b43_gphy_op_interf_mitigation()
2719 gphy->aci_wlan_automatic = true; in b43_gphy_op_interf_mitigation()
2720 if (gphy->aci_enable) in b43_gphy_op_interf_mitigation()
2730 return -EINVAL; in b43_gphy_op_interf_mitigation()
2733 currentmode = gphy->interfmode; in b43_gphy_op_interf_mitigation()
2735 return 0; in b43_gphy_op_interf_mitigation()
2737 b43_radio_interference_mitigation_disable(dev, currentmode); in b43_gphy_op_interf_mitigation()
2740 gphy->aci_enable = false; in b43_gphy_op_interf_mitigation()
2741 gphy->aci_hw_rssi = false; in b43_gphy_op_interf_mitigation()
2743 b43_radio_interference_mitigation_enable(dev, mode); in b43_gphy_op_interf_mitigation()
2744 gphy->interfmode = mode; in b43_gphy_op_interf_mitigation()
2746 return 0; in b43_gphy_op_interf_mitigation()
2749 /* https://bcm-specs.sipsolutions.net/EstimatePowerOut
2752 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) in b43_gphy_estimate_power_out() argument
2754 struct b43_phy_g *gphy = dev->phy.g; in b43_gphy_estimate_power_out()
2758 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi); in b43_gphy_estimate_power_out()
2759 tmp = clamp_val(tmp, 0x00, 0x3F); in b43_gphy_estimate_power_out()
2760 dbm = gphy->tssi2dbm[tmp]; in b43_gphy_estimate_power_out()
2765 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev, in b43_put_attenuation_into_ranges() argument
2770 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; in b43_put_attenuation_into_ranges()
2776 const int rf_min = lo->rfatt_list.min_val; in b43_put_attenuation_into_ranges()
2777 const int rf_max = lo->rfatt_list.max_val; in b43_put_attenuation_into_ranges()
2778 const int bb_min = lo->bbatt_list.min_val; in b43_put_attenuation_into_ranges()
2779 const int bb_max = lo->bbatt_list.max_val; in b43_put_attenuation_into_ranges()
2782 if (rfatt > rf_max && bbatt > bb_max - 4) in b43_put_attenuation_into_ranges()
2786 if (bbatt > bb_max && rfatt > rf_max - 1) in b43_put_attenuation_into_ranges()
2792 bbatt -= 4; in b43_put_attenuation_into_ranges()
2798 rfatt -= 1; in b43_put_attenuation_into_ranges()
2802 rfatt -= 1; in b43_put_attenuation_into_ranges()
2808 bbatt -= 4; in b43_put_attenuation_into_ranges()
2818 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev) in b43_gphy_op_adjust_txpower() argument
2820 struct b43_phy *phy = &dev->phy; in b43_gphy_op_adjust_txpower()
2821 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_adjust_txpower()
2825 b43_mac_suspend(dev); in b43_gphy_op_adjust_txpower()
2828 bbatt = gphy->bbatt.att; in b43_gphy_op_adjust_txpower()
2829 bbatt += gphy->bbatt_delta; in b43_gphy_op_adjust_txpower()
2830 rfatt = gphy->rfatt.att; in b43_gphy_op_adjust_txpower()
2831 rfatt += gphy->rfatt_delta; in b43_gphy_op_adjust_txpower()
2833 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2834 tx_control = gphy->tx_control; in b43_gphy_op_adjust_txpower()
2835 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) { in b43_gphy_op_adjust_txpower()
2837 if (tx_control == 0) { in b43_gphy_op_adjust_txpower()
2843 } else if (dev->dev->bus_sprom-> in b43_gphy_op_adjust_txpower()
2846 bbatt += 4 * (rfatt - 2); in b43_gphy_op_adjust_txpower()
2850 tx_control = 0; in b43_gphy_op_adjust_txpower()
2852 rfatt -= 3; in b43_gphy_op_adjust_txpower()
2855 rfatt -= 2; in b43_gphy_op_adjust_txpower()
2856 bbatt -= 2; in b43_gphy_op_adjust_txpower()
2861 gphy->tx_control = tx_control; in b43_gphy_op_adjust_txpower()
2862 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); in b43_gphy_op_adjust_txpower()
2863 gphy->rfatt.att = rfatt; in b43_gphy_op_adjust_txpower()
2864 gphy->bbatt.att = bbatt; in b43_gphy_op_adjust_txpower()
2866 if (b43_debug(dev, B43_DBG_XMITPOWER)) in b43_gphy_op_adjust_txpower()
2867 b43dbg(dev->wl, "Adjusting TX power\n"); in b43_gphy_op_adjust_txpower()
2870 b43_phy_lock(dev); in b43_gphy_op_adjust_txpower()
2871 b43_radio_lock(dev); in b43_gphy_op_adjust_txpower()
2872 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, in b43_gphy_op_adjust_txpower()
2873 gphy->tx_control); in b43_gphy_op_adjust_txpower()
2874 b43_radio_unlock(dev); in b43_gphy_op_adjust_txpower()
2875 b43_phy_unlock(dev); in b43_gphy_op_adjust_txpower()
2877 b43_mac_enable(dev); in b43_gphy_op_adjust_txpower()
2880 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev, in b43_gphy_op_recalc_txpower() argument
2883 struct b43_phy *phy = &dev->phy; in b43_gphy_op_recalc_txpower()
2884 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_recalc_txpower()
2892 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK); in b43_gphy_op_recalc_txpower()
2893 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G); in b43_gphy_op_recalc_txpower()
2894 if ((cck_result < 0) && (ofdm_result < 0)) { in b43_gphy_op_recalc_txpower()
2898 cck_result = 0; in b43_gphy_op_recalc_txpower()
2899 ofdm_result = 0; in b43_gphy_op_recalc_txpower()
2901 if (cck_result < 0) in b43_gphy_op_recalc_txpower()
2903 else if (ofdm_result < 0) in b43_gphy_op_recalc_txpower()
2908 if (likely(gphy->average_tssi != 0xFF)) in b43_gphy_op_recalc_txpower()
2909 average_tssi = (average_tssi + gphy->average_tssi) / 2; in b43_gphy_op_recalc_txpower()
2910 gphy->average_tssi = average_tssi; in b43_gphy_op_recalc_txpower()
2914 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); in b43_gphy_op_recalc_txpower()
2916 B43_WARN_ON(phy->type != B43_PHYTYPE_G); in b43_gphy_op_recalc_txpower()
2917 max_pwr = dev->dev->bus_sprom->maxpwr_bg; in b43_gphy_op_recalc_txpower()
2918 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) in b43_gphy_op_recalc_txpower()
2919 max_pwr -= 3; /* minus 0.75 */ in b43_gphy_op_recalc_txpower()
2921 b43warn(dev->wl, in b43_gphy_op_recalc_txpower()
2922 "Invalid max-TX-power value in SPROM.\n"); in b43_gphy_op_recalc_txpower()
2924 dev->dev->bus_sprom->maxpwr_bg = max_pwr; in b43_gphy_op_recalc_txpower()
2928 if (phy->desired_txpower < 0) in b43_gphy_op_recalc_txpower()
2929 desired_pwr = INT_TO_Q52(0); in b43_gphy_op_recalc_txpower()
2931 desired_pwr = INT_TO_Q52(phy->desired_txpower); in b43_gphy_op_recalc_txpower()
2933 desired_pwr = clamp_val(desired_pwr, 0, max_pwr); in b43_gphy_op_recalc_txpower()
2934 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2935 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
2945 pwr_adjust = desired_pwr - estimated_pwr; in b43_gphy_op_recalc_txpower()
2946 if (pwr_adjust == 0) in b43_gphy_op_recalc_txpower()
2952 rfatt_delta = -rfatt_delta; in b43_gphy_op_recalc_txpower()
2957 bbatt_delta = -bbatt_delta; in b43_gphy_op_recalc_txpower()
2960 bbatt_delta -= 4 * rfatt_delta; in b43_gphy_op_recalc_txpower()
2963 if (b43_debug(dev, B43_DBG_XMITPOWER)) { in b43_gphy_op_recalc_txpower()
2964 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust; in b43_gphy_op_recalc_txpower()
2965 b43dbg(dev->wl, in b43_gphy_op_recalc_txpower()
2967 "bbatt-delta = %d, rfatt-delta = %d\n", in b43_gphy_op_recalc_txpower()
2968 (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm), in b43_gphy_op_recalc_txpower()
2974 if ((rfatt_delta == 0) && (bbatt_delta == 0)) in b43_gphy_op_recalc_txpower()
2978 gphy->bbatt_delta = bbatt_delta; in b43_gphy_op_recalc_txpower()
2979 gphy->rfatt_delta = rfatt_delta; in b43_gphy_op_recalc_txpower()
2988 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev) in b43_gphy_op_pwork_15sec() argument
2990 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_15sec()
2991 struct b43_phy_g *gphy = phy->g; in b43_gphy_op_pwork_15sec()
2993 b43_mac_suspend(dev); in b43_gphy_op_pwork_15sec()
2995 if (gphy->aci_enable && gphy->aci_wlan_automatic) { in b43_gphy_op_pwork_15sec()
2996 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) { in b43_gphy_op_pwork_15sec()
2997 if (0 /*TODO: bunch of conditions */ ) { in b43_gphy_op_pwork_15sec()
2998 phy->ops->interf_mitigation(dev, in b43_gphy_op_pwork_15sec()
3001 } else if (0 /*TODO*/) { in b43_gphy_op_pwork_15sec()
3002 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev)) in b43_gphy_op_pwork_15sec()
3003 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); in b43_gphy_op_pwork_15sec()
3005 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN && in b43_gphy_op_pwork_15sec()
3006 phy->rev == 1) { in b43_gphy_op_pwork_15sec()
3009 b43_lo_g_maintenance_work(dev); in b43_gphy_op_pwork_15sec()
3010 b43_mac_enable(dev); in b43_gphy_op_pwork_15sec()
3013 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev) in b43_gphy_op_pwork_60sec() argument
3015 struct b43_phy *phy = &dev->phy; in b43_gphy_op_pwork_60sec()
3017 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) in b43_gphy_op_pwork_60sec()
3020 b43_mac_suspend(dev); in b43_gphy_op_pwork_60sec()
3021 b43_calc_nrssi_slope(dev); in b43_gphy_op_pwork_60sec()
3022 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { in b43_gphy_op_pwork_60sec()
3023 u8 old_chan = phy->channel; in b43_gphy_op_pwork_60sec()
3027 b43_switch_channel(dev, 1); in b43_gphy_op_pwork_60sec()
3029 b43_switch_channel(dev, 13); in b43_gphy_op_pwork_60sec()
3030 b43_switch_channel(dev, old_chan); in b43_gphy_op_pwork_60sec()
3032 b43_mac_enable(dev); in b43_gphy_op_pwork_60sec()