97 	B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));  in op32_fill_descriptor()
189 	B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));  in op64_fill_descriptor()
264 	B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));  in next_slot()
272 	B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));  in prev_slot()
304 	B43_WARN_ON(!ring->tx);  in request_slot()
305 	B43_WARN_ON(ring->stopped);  in request_slot()
306 	B43_WARN_ON(free_slots(ring) == 0);  in request_slot()
337 		B43_WARN_ON(!(controller_idx >= 0 &&  in b43_dmacontroller_base()
341 	B43_WARN_ON(!(controller_idx >= 0 &&  in b43_dmacontroller_base()
380 	B43_WARN_ON(ring->tx);  in sync_descbuffer_for_cpu()
389 	B43_WARN_ON(ring->tx);  in sync_descbuffer_for_device()
587 	B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);  in b43_poison_rx_buffer()
599 	B43_WARN_ON(ring->tx);  in setup_rx_descbuffer()
786 			B43_WARN_ON(!ring->tx);  in free_all_descbuffers()
881 			B43_WARN_ON(1);  in b43_setup_dmaring()
1114 	B43_WARN_ON(dev->dev->core_rev < 5);  in b43_dma_init()
1149 	B43_WARN_ON(slot & ~0x0FFF);  in generate_cookie()
1319 			B43_WARN_ON(1);  in select_ring_by_priority()
1360 	B43_WARN_ON(!ring->tx);  in b43_dma_tx()
1430 	B43_WARN_ON(!ring->tx);  in b43_dma_handle_txstatus()
1474 		B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);  in b43_dma_handle_txstatus()
1564 		B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);  in b43_dma_handle_txstatus()
1672 	B43_WARN_ON(ring->tx);  in b43_dma_handle_rx_overflow()
1693 	B43_WARN_ON(ring->tx);  in b43_dma_rx()
1695 	B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));  in b43_dma_rx()
1709 	B43_WARN_ON(!ring->tx);  in b43_dma_tx_suspend_ring()
1715 	B43_WARN_ON(!ring->tx);  in b43_dma_tx_resume_ring()