Lines Matching refs:q
46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) in ath9k_hw_gettxbuf() argument
48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) in ath9k_hw_puttxbuf() argument
54 REG_WRITE(ah, AR_QTXDP(q), txdp); in ath9k_hw_puttxbuf()
58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q) in ath9k_hw_txstart() argument
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); in ath9k_hw_txstart()
61 REG_WRITE(ah, AR_Q_TXE, 1 << q); in ath9k_hw_txstart()
65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) in ath9k_hw_numtxpending() argument
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
137 int i, q; in ath9k_hw_abort_tx_dma() local
152 for (q = 0; q < AR_NUM_QCU; q++) { in ath9k_hw_abort_tx_dma()
157 if (!ath9k_hw_numtxpending(ah, q)) in ath9k_hw_abort_tx_dma()
170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) in ath9k_hw_stop_dma_queue() argument
177 REG_WRITE(ah, AR_Q_TXD, 1 << q); in ath9k_hw_stop_dma_queue()
183 if (ath9k_hw_numtxpending(ah, q) == 0) in ath9k_hw_stop_dma_queue()
196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, in ath9k_hw_set_txq_props() argument
203 qi = &ah->txq[q]; in ath9k_hw_set_txq_props()
206 "Set TXQ properties, inactive queue: %u\n", q); in ath9k_hw_set_txq_props()
210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); in ath9k_hw_set_txq_props()
261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, in ath9k_hw_get_txq_props() argument
267 qi = &ah->txq[q]; in ath9k_hw_get_txq_props()
270 "Get TXQ properties, inactive queue: %u\n", q); in ath9k_hw_get_txq_props()
298 int q; in ath9k_hw_setuptxqueue() local
302 q = ATH9K_NUM_TX_QUEUES - 1; in ath9k_hw_setuptxqueue()
305 q = ATH9K_NUM_TX_QUEUES - 2; in ath9k_hw_setuptxqueue()
308 q = 1; in ath9k_hw_setuptxqueue()
311 q = ATH9K_NUM_TX_QUEUES - 3; in ath9k_hw_setuptxqueue()
314 q = qinfo->tqi_subtype; in ath9k_hw_setuptxqueue()
321 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); in ath9k_hw_setuptxqueue()
323 qi = &ah->txq[q]; in ath9k_hw_setuptxqueue()
325 ath_err(common, "TX queue: %u already active\n", q); in ath9k_hw_setuptxqueue()
331 (void) ath9k_hw_set_txq_props(ah, q, qinfo); in ath9k_hw_setuptxqueue()
333 return q; in ath9k_hw_setuptxqueue()
337 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) in ath9k_hw_clear_queue_interrupts() argument
339 ah->txok_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
340 ah->txerr_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
341 ah->txdesc_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
342 ah->txeol_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
343 ah->txurn_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
346 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) in ath9k_hw_releasetxqueue() argument
351 qi = &ah->txq[q]; in ath9k_hw_releasetxqueue()
353 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); in ath9k_hw_releasetxqueue()
357 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); in ath9k_hw_releasetxqueue()
360 ath9k_hw_clear_queue_interrupts(ah, q); in ath9k_hw_releasetxqueue()
367 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) in ath9k_hw_resettxqueue() argument
373 qi = &ah->txq[q]; in ath9k_hw_resettxqueue()
375 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); in ath9k_hw_resettxqueue()
379 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); in ath9k_hw_resettxqueue()
390 REG_WRITE(ah, AR_DLCL_IFS(q), in ath9k_hw_resettxqueue()
395 REG_WRITE(ah, AR_DRETRY_LIMIT(q), in ath9k_hw_resettxqueue()
400 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ath9k_hw_resettxqueue()
403 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
406 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
410 REG_WRITE(ah, AR_QCBRCFG(q), in ath9k_hw_resettxqueue()
413 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
418 REG_WRITE(ah, AR_QRDYTIMECFG(q), in ath9k_hw_resettxqueue()
423 REG_WRITE(ah, AR_DCHNTIME(q), in ath9k_hw_resettxqueue()
429 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); in ath9k_hw_resettxqueue()
432 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
437 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
443 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
448 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
463 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) in ath9k_hw_resettxqueue()
471 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
478 REG_WRITE(ah, AR_QRDYTIMECFG(q), in ath9k_hw_resettxqueue()
480 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
488 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); in ath9k_hw_resettxqueue()
491 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
498 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
507 ath9k_hw_clear_queue_interrupts(ah, q); in ath9k_hw_resettxqueue()
509 ah->txok_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
510 ah->txerr_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
513 ah->txdesc_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
515 ah->txeol_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
517 ah->txurn_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()