Lines Matching +full:rx +full:- +full:inactive
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; in ath9k_hw_set_txq_interrupts()
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); in ath9k_hw_set_txq_interrupts()
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_txq_interrupts()
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level) in ath9k_hw_updatetxtriglevel()
118 if (curLevel < ah->config.max_txtrig_level) in ath9k_hw_updatetxtriglevel()
121 newLevel--; in ath9k_hw_updatetxtriglevel()
128 ah->tx_trig_level = newLevel; in ath9k_hw_updatetxtriglevel()
139 if (ah->curchan) { in ath9k_hw_abort_tx_dma()
140 if (IS_CHAN_HALF_RATE(ah->curchan)) in ath9k_hw_abort_tx_dma()
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan)) in ath9k_hw_abort_tx_dma()
179 for (wait = wait_time; wait != 0; wait--) { in ath9k_hw_stop_dma_queue()
203 qi = &ah->txq[q]; in ath9k_hw_set_txq_props()
204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { in ath9k_hw_set_txq_props()
206 "Set TXQ properties, inactive queue: %u\n", q); in ath9k_hw_set_txq_props()
212 qi->tqi_ver = qinfo->tqi_ver; in ath9k_hw_set_txq_props()
213 qi->tqi_subtype = qinfo->tqi_subtype; in ath9k_hw_set_txq_props()
214 qi->tqi_qflags = qinfo->tqi_qflags; in ath9k_hw_set_txq_props()
215 qi->tqi_priority = qinfo->tqi_priority; in ath9k_hw_set_txq_props()
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) in ath9k_hw_set_txq_props()
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); in ath9k_hw_set_txq_props()
219 qi->tqi_aifs = INIT_AIFS; in ath9k_hw_set_txq_props()
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { in ath9k_hw_set_txq_props()
221 cw = min(qinfo->tqi_cwmin, 1024U); in ath9k_hw_set_txq_props()
222 qi->tqi_cwmin = 1; in ath9k_hw_set_txq_props()
223 while (qi->tqi_cwmin < cw) in ath9k_hw_set_txq_props()
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; in ath9k_hw_set_txq_props()
226 qi->tqi_cwmin = qinfo->tqi_cwmin; in ath9k_hw_set_txq_props()
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { in ath9k_hw_set_txq_props()
228 cw = min(qinfo->tqi_cwmax, 1024U); in ath9k_hw_set_txq_props()
229 qi->tqi_cwmax = 1; in ath9k_hw_set_txq_props()
230 while (qi->tqi_cwmax < cw) in ath9k_hw_set_txq_props()
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; in ath9k_hw_set_txq_props()
233 qi->tqi_cwmax = INIT_CWMAX; in ath9k_hw_set_txq_props()
235 if (qinfo->tqi_shretry != 0) in ath9k_hw_set_txq_props()
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); in ath9k_hw_set_txq_props()
238 qi->tqi_shretry = INIT_SH_RETRY; in ath9k_hw_set_txq_props()
239 if (qinfo->tqi_lgretry != 0) in ath9k_hw_set_txq_props()
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); in ath9k_hw_set_txq_props()
242 qi->tqi_lgretry = INIT_LG_RETRY; in ath9k_hw_set_txq_props()
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; in ath9k_hw_set_txq_props()
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; in ath9k_hw_set_txq_props()
245 qi->tqi_burstTime = qinfo->tqi_burstTime; in ath9k_hw_set_txq_props()
246 qi->tqi_readyTime = qinfo->tqi_readyTime; in ath9k_hw_set_txq_props()
248 switch (qinfo->tqi_subtype) { in ath9k_hw_set_txq_props()
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) in ath9k_hw_set_txq_props()
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; in ath9k_hw_set_txq_props()
267 qi = &ah->txq[q]; in ath9k_hw_get_txq_props()
268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { in ath9k_hw_get_txq_props()
270 "Get TXQ properties, inactive queue: %u\n", q); in ath9k_hw_get_txq_props()
274 qinfo->tqi_qflags = qi->tqi_qflags; in ath9k_hw_get_txq_props()
275 qinfo->tqi_ver = qi->tqi_ver; in ath9k_hw_get_txq_props()
276 qinfo->tqi_subtype = qi->tqi_subtype; in ath9k_hw_get_txq_props()
277 qinfo->tqi_qflags = qi->tqi_qflags; in ath9k_hw_get_txq_props()
278 qinfo->tqi_priority = qi->tqi_priority; in ath9k_hw_get_txq_props()
279 qinfo->tqi_aifs = qi->tqi_aifs; in ath9k_hw_get_txq_props()
280 qinfo->tqi_cwmin = qi->tqi_cwmin; in ath9k_hw_get_txq_props()
281 qinfo->tqi_cwmax = qi->tqi_cwmax; in ath9k_hw_get_txq_props()
282 qinfo->tqi_shretry = qi->tqi_shretry; in ath9k_hw_get_txq_props()
283 qinfo->tqi_lgretry = qi->tqi_lgretry; in ath9k_hw_get_txq_props()
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; in ath9k_hw_get_txq_props()
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; in ath9k_hw_get_txq_props()
286 qinfo->tqi_burstTime = qi->tqi_burstTime; in ath9k_hw_get_txq_props()
287 qinfo->tqi_readyTime = qi->tqi_readyTime; in ath9k_hw_get_txq_props()
302 q = ATH9K_NUM_TX_QUEUES - 1; in ath9k_hw_setuptxqueue()
305 q = ATH9K_NUM_TX_QUEUES - 2; in ath9k_hw_setuptxqueue()
311 q = ATH9K_NUM_TX_QUEUES - 3; in ath9k_hw_setuptxqueue()
314 q = qinfo->tqi_subtype; in ath9k_hw_setuptxqueue()
318 return -1; in ath9k_hw_setuptxqueue()
323 qi = &ah->txq[q]; in ath9k_hw_setuptxqueue()
324 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { in ath9k_hw_setuptxqueue()
326 return -1; in ath9k_hw_setuptxqueue()
329 qi->tqi_type = type; in ath9k_hw_setuptxqueue()
330 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; in ath9k_hw_setuptxqueue()
339 ah->txok_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
340 ah->txerr_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
341 ah->txdesc_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
342 ah->txeol_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
343 ah->txurn_interrupt_mask &= ~(1 << q); in ath9k_hw_clear_queue_interrupts()
351 qi = &ah->txq[q]; in ath9k_hw_releasetxqueue()
352 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { in ath9k_hw_releasetxqueue()
353 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); in ath9k_hw_releasetxqueue()
359 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; in ath9k_hw_releasetxqueue()
373 qi = &ah->txq[q]; in ath9k_hw_resettxqueue()
374 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { in ath9k_hw_resettxqueue()
375 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); in ath9k_hw_resettxqueue()
381 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { in ath9k_hw_resettxqueue()
386 cwMin = qi->tqi_cwmin; in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
398 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); in ath9k_hw_resettxqueue()
409 if (qi->tqi_cbrPeriod) { in ath9k_hw_resettxqueue()
411 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | in ath9k_hw_resettxqueue()
412 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); in ath9k_hw_resettxqueue()
414 (qi->tqi_cbrOverflowLimit ? in ath9k_hw_resettxqueue()
417 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { in ath9k_hw_resettxqueue()
419 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | in ath9k_hw_resettxqueue()
424 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | in ath9k_hw_resettxqueue()
425 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); in ath9k_hw_resettxqueue()
427 if (qi->tqi_burstTime in ath9k_hw_resettxqueue()
428 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) in ath9k_hw_resettxqueue()
431 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) in ath9k_hw_resettxqueue()
436 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) in ath9k_hw_resettxqueue()
439 switch (qi->tqi_type) { in ath9k_hw_resettxqueue()
462 ah->opmode != NL80211_IFTYPE_ADHOC) { in ath9k_hw_resettxqueue()
465 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
475 value = (qi->tqi_readyTime - in ath9k_hw_resettxqueue()
476 (ah->config.sw_beacon_response_time - in ath9k_hw_resettxqueue()
477 ah->config.dma_beacon_response_time)) * 1024; in ath9k_hw_resettxqueue()
497 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { in ath9k_hw_resettxqueue()
508 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) { in ath9k_hw_resettxqueue()
509 ah->txok_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
510 ah->txerr_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
512 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) in ath9k_hw_resettxqueue()
513 ah->txdesc_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
514 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) in ath9k_hw_resettxqueue()
515 ah->txeol_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
516 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) in ath9k_hw_resettxqueue()
517 ah->txurn_interrupt_mask |= 1 << q; in ath9k_hw_resettxqueue()
531 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) in ath9k_hw_rxprocdesc()
532 return -EINPROGRESS; in ath9k_hw_rxprocdesc()
534 ads.u.rx = adsp->u.rx; in ath9k_hw_rxprocdesc()
536 rs->rs_status = 0; in ath9k_hw_rxprocdesc()
537 rs->rs_flags = 0; in ath9k_hw_rxprocdesc()
538 rs->enc_flags = 0; in ath9k_hw_rxprocdesc()
539 rs->bw = RATE_INFO_BW_20; in ath9k_hw_rxprocdesc()
541 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; in ath9k_hw_rxprocdesc()
542 rs->rs_tstamp = ads.AR_RcvTimestamp; in ath9k_hw_rxprocdesc()
545 rs->rs_rssi = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
546 rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
547 rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
548 rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
549 rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
550 rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
551 rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD; in ath9k_hw_rxprocdesc()
553 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); in ath9k_hw_rxprocdesc()
554 rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
556 rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
558 rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
560 rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
562 rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
564 rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
568 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); in ath9k_hw_rxprocdesc()
570 rs->rs_keyix = ATH9K_RXKEYIX_INVALID; in ath9k_hw_rxprocdesc()
572 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); in ath9k_hw_rxprocdesc()
573 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; in ath9k_hw_rxprocdesc()
575 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0; in ath9k_hw_rxprocdesc()
576 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; in ath9k_hw_rxprocdesc()
577 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; in ath9k_hw_rxprocdesc()
578 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); in ath9k_hw_rxprocdesc()
581 rs->enc_flags |= in ath9k_hw_rxprocdesc()
583 rs->bw = (ads.ds_rxstatus3 & AR_2040) ? RATE_INFO_BW_40 : in ath9k_hw_rxprocdesc()
586 rs->enc_flags |= in ath9k_hw_rxprocdesc()
592 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; in ath9k_hw_rxprocdesc()
594 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; in ath9k_hw_rxprocdesc()
596 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; in ath9k_hw_rxprocdesc()
606 rs->rs_status |= ATH9K_RXERR_PHY; in ath9k_hw_rxprocdesc()
608 rs->rs_phyerr = phyerr; in ath9k_hw_rxprocdesc()
610 rs->rs_status |= ATH9K_RXERR_CRC; in ath9k_hw_rxprocdesc()
612 rs->rs_status |= ATH9K_RXERR_DECRYPT; in ath9k_hw_rxprocdesc()
614 rs->rs_status |= ATH9K_RXERR_MIC; in ath9k_hw_rxprocdesc()
618 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; in ath9k_hw_rxprocdesc()
621 if (rs->rs_rate >= 0x90) in ath9k_hw_rxprocdesc()
622 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; in ath9k_hw_rxprocdesc()
626 rs->rs_status |= ATH9K_RXERR_KEYMISS; in ath9k_hw_rxprocdesc()
633 * This can stop or re-enables RX.
655 "RX failed to go idle in 10 ms RXSM=0x%x\n", in ath9k_hw_setrxabort()
708 /* Wait for rx enable bit to go low */ in ath9k_hw_stopdmarecv()
709 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) { in ath9k_hw_stopdmarecv()
751 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) in ath9k_hw_beaconq_setup()
800 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_disable_interrupts()
801 atomic_set(&ah->intr_ref_cnt, -1); in ath9k_hw_disable_interrupts()
803 atomic_dec(&ah->intr_ref_cnt); in ath9k_hw_disable_interrupts()
821 if (ah->imask & ATH9K_INT_MCI) in __ath9k_hw_enable_interrupts()
836 if (ah->msi_enabled) { in __ath9k_hw_enable_interrupts()
842 "Enabling MSI, msi_mask=0x%X\n", ah->msi_mask); in __ath9k_hw_enable_interrupts()
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), ah->msi_mask); in __ath9k_hw_enable_interrupts()
845 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), ah->msi_mask); in __ath9k_hw_enable_interrupts()
851 if (ah->msi_reg == 0) in __ath9k_hw_enable_interrupts()
852 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah)); in __ath9k_hw_enable_interrupts()
855 "AR_PCIE_MSI=0x%X, ah->msi_reg = 0x%X\n", in __ath9k_hw_enable_interrupts()
856 AR_PCIE_MSI(ah), ah->msi_reg); in __ath9k_hw_enable_interrupts()
861 (ah->msi_reg | AR_PCIE_MSI_ENABLE) in __ath9k_hw_enable_interrupts()
878 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_resume_interrupts()
881 if (atomic_read(&ah->intr_ref_cnt) != 0) { in ath9k_hw_resume_interrupts()
883 atomic_read(&ah->intr_ref_cnt)); in ath9k_hw_resume_interrupts()
895 if (!(ah->imask & ATH9K_INT_GLOBAL)) in ath9k_hw_enable_interrupts()
898 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { in ath9k_hw_enable_interrupts()
900 atomic_read(&ah->intr_ref_cnt)); in ath9k_hw_enable_interrupts()
910 enum ath9k_int ints = ah->imask; in ath9k_hw_set_interrupts()
912 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_interrupts()
918 if (ah->msi_enabled) { in ath9k_hw_set_interrupts()
930 ah->msi_mask = 0; in ath9k_hw_set_interrupts()
932 ah->msi_mask |= AR_INTR_PRIO_TX; in ath9k_hw_set_interrupts()
933 if (ah->config.tx_intr_mitigation) in ath9k_hw_set_interrupts()
936 if (ah->txok_interrupt_mask) in ath9k_hw_set_interrupts()
938 if (ah->txdesc_interrupt_mask) in ath9k_hw_set_interrupts()
941 if (ah->txerr_interrupt_mask) in ath9k_hw_set_interrupts()
943 if (ah->txeol_interrupt_mask) in ath9k_hw_set_interrupts()
947 ah->msi_mask |= AR_INTR_PRIO_RXLP | AR_INTR_PRIO_RXHP; in ath9k_hw_set_interrupts()
950 if (ah->config.rx_intr_mitigation) { in ath9k_hw_set_interrupts()
957 if (ah->config.rx_intr_mitigation) in ath9k_hw_set_interrupts()
962 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) in ath9k_hw_set_interrupts()
991 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { in ath9k_hw_set_interrupts()
1000 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | in ath9k_hw_set_interrupts()
1009 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { in ath9k_hw_set_interrupts()
1011 ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
1014 ah->imrs2_reg |= mask2; in ath9k_hw_set_interrupts()
1015 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_set_interrupts()
1017 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { in ath9k_hw_set_interrupts()