Lines Matching refs:REG_CLR_BIT
740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
1286 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1414 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1695 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
2102 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2103 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2104 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2124 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2160 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2166 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2225 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2909 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
3188 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3216 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3224 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3230 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()