Lines Matching refs:PR_EEP
138 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); in ath9k_def_dump_modal_eeprom()
139 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); in ath9k_def_dump_modal_eeprom()
140 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); in ath9k_def_dump_modal_eeprom()
141 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ath9k_def_dump_modal_eeprom()
142 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); in ath9k_def_dump_modal_eeprom()
143 PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]); in ath9k_def_dump_modal_eeprom()
144 PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]); in ath9k_def_dump_modal_eeprom()
145 PR_EEP("Switch Settle", modal_hdr->switchSettling); in ath9k_def_dump_modal_eeprom()
146 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); in ath9k_def_dump_modal_eeprom()
147 PR_EEP("Chain1 TxRxAtten", modal_hdr->txRxAttenCh[1]); in ath9k_def_dump_modal_eeprom()
148 PR_EEP("Chain2 TxRxAtten", modal_hdr->txRxAttenCh[2]); in ath9k_def_dump_modal_eeprom()
149 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); in ath9k_def_dump_modal_eeprom()
150 PR_EEP("Chain1 RxTxMargin", modal_hdr->rxTxMarginCh[1]); in ath9k_def_dump_modal_eeprom()
151 PR_EEP("Chain2 RxTxMargin", modal_hdr->rxTxMarginCh[2]); in ath9k_def_dump_modal_eeprom()
152 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); in ath9k_def_dump_modal_eeprom()
153 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize); in ath9k_def_dump_modal_eeprom()
154 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]); in ath9k_def_dump_modal_eeprom()
155 PR_EEP("Chain1 xlna Gain", modal_hdr->xlnaGainCh[1]); in ath9k_def_dump_modal_eeprom()
156 PR_EEP("Chain2 xlna Gain", modal_hdr->xlnaGainCh[2]); in ath9k_def_dump_modal_eeprom()
157 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); in ath9k_def_dump_modal_eeprom()
158 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); in ath9k_def_dump_modal_eeprom()
159 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); in ath9k_def_dump_modal_eeprom()
160 PR_EEP("CCA Threshold)", modal_hdr->thresh62); in ath9k_def_dump_modal_eeprom()
161 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); in ath9k_def_dump_modal_eeprom()
162 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); in ath9k_def_dump_modal_eeprom()
163 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); in ath9k_def_dump_modal_eeprom()
164 PR_EEP("xpdGain", modal_hdr->xpdGain); in ath9k_def_dump_modal_eeprom()
165 PR_EEP("External PD", modal_hdr->xpd); in ath9k_def_dump_modal_eeprom()
166 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); in ath9k_def_dump_modal_eeprom()
167 PR_EEP("Chain1 I Coefficient", modal_hdr->iqCalICh[1]); in ath9k_def_dump_modal_eeprom()
168 PR_EEP("Chain2 I Coefficient", modal_hdr->iqCalICh[2]); in ath9k_def_dump_modal_eeprom()
169 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); in ath9k_def_dump_modal_eeprom()
170 PR_EEP("Chain1 Q Coefficient", modal_hdr->iqCalQCh[1]); in ath9k_def_dump_modal_eeprom()
171 PR_EEP("Chain2 Q Coefficient", modal_hdr->iqCalQCh[2]); in ath9k_def_dump_modal_eeprom()
172 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); in ath9k_def_dump_modal_eeprom()
173 PR_EEP("Chain0 OutputBias", modal_hdr->ob); in ath9k_def_dump_modal_eeprom()
174 PR_EEP("Chain0 DriverBias", modal_hdr->db); in ath9k_def_dump_modal_eeprom()
175 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); in ath9k_def_dump_modal_eeprom()
176 PR_EEP("2chain pwr decrease", modal_hdr->pwrDecreaseFor2Chain); in ath9k_def_dump_modal_eeprom()
177 PR_EEP("3chain pwr decrease", modal_hdr->pwrDecreaseFor3Chain); in ath9k_def_dump_modal_eeprom()
178 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); in ath9k_def_dump_modal_eeprom()
179 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); in ath9k_def_dump_modal_eeprom()
180 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); in ath9k_def_dump_modal_eeprom()
181 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); in ath9k_def_dump_modal_eeprom()
182 PR_EEP("Chain1 bswAtten", modal_hdr->bswAtten[1]); in ath9k_def_dump_modal_eeprom()
183 PR_EEP("Chain2 bswAtten", modal_hdr->bswAtten[2]); in ath9k_def_dump_modal_eeprom()
184 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); in ath9k_def_dump_modal_eeprom()
185 PR_EEP("Chain1 bswMargin", modal_hdr->bswMargin[1]); in ath9k_def_dump_modal_eeprom()
186 PR_EEP("Chain2 bswMargin", modal_hdr->bswMargin[2]); in ath9k_def_dump_modal_eeprom()
187 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); in ath9k_def_dump_modal_eeprom()
188 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]); in ath9k_def_dump_modal_eeprom()
189 PR_EEP("Chain1 xatten2Db", modal_hdr->xatten2Db[1]); in ath9k_def_dump_modal_eeprom()
190 PR_EEP("Chain2 xatten2Db", modal_hdr->xatten2Db[2]); in ath9k_def_dump_modal_eeprom()
191 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]); in ath9k_def_dump_modal_eeprom()
192 PR_EEP("Chain1 xatten2Margin", modal_hdr->xatten2Margin[1]); in ath9k_def_dump_modal_eeprom()
193 PR_EEP("Chain2 xatten2Margin", modal_hdr->xatten2Margin[2]); in ath9k_def_dump_modal_eeprom()
194 PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1); in ath9k_def_dump_modal_eeprom()
195 PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1); in ath9k_def_dump_modal_eeprom()
196 PR_EEP("LNA Control", modal_hdr->lna_ctl); in ath9k_def_dump_modal_eeprom()
197 PR_EEP("XPA Bias Freq0", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[0])); in ath9k_def_dump_modal_eeprom()
198 PR_EEP("XPA Bias Freq1", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[1])); in ath9k_def_dump_modal_eeprom()
199 PR_EEP("XPA Bias Freq2", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[2])); in ath9k_def_dump_modal_eeprom()
223 PR_EEP("Major Version", ath9k_hw_def_get_eeprom_ver(ah)); in ath9k_hw_def_dump_eeprom()
224 PR_EEP("Minor Version", ath9k_hw_def_get_eeprom_rev(ah)); in ath9k_hw_def_dump_eeprom()
225 PR_EEP("Checksum", le16_to_cpu(pBase->checksum)); in ath9k_hw_def_dump_eeprom()
226 PR_EEP("Length", le16_to_cpu(pBase->length)); in ath9k_hw_def_dump_eeprom()
227 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); in ath9k_hw_def_dump_eeprom()
228 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); in ath9k_hw_def_dump_eeprom()
229 PR_EEP("TX Mask", pBase->txMask); in ath9k_hw_def_dump_eeprom()
230 PR_EEP("RX Mask", pBase->rxMask); in ath9k_hw_def_dump_eeprom()
231 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); in ath9k_hw_def_dump_eeprom()
232 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); in ath9k_hw_def_dump_eeprom()
233 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & in ath9k_hw_def_dump_eeprom()
235 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & in ath9k_hw_def_dump_eeprom()
237 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & in ath9k_hw_def_dump_eeprom()
239 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & in ath9k_hw_def_dump_eeprom()
241 PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN)); in ath9k_hw_def_dump_eeprom()
242 PR_EEP("Cal Bin Major Ver", (binBuildNumber >> 24) & 0xFF); in ath9k_hw_def_dump_eeprom()
243 PR_EEP("Cal Bin Minor Ver", (binBuildNumber >> 16) & 0xFF); in ath9k_hw_def_dump_eeprom()
244 PR_EEP("Cal Bin Build", (binBuildNumber >> 8) & 0xFF); in ath9k_hw_def_dump_eeprom()
245 PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl); in ath9k_hw_def_dump_eeprom()