Lines Matching +full:channel +full:- +full:spacing
2 * Copyright (c) 2010-2011 Atheros Communications, Inc.
21 * Channel Register Map
88 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
89 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
101 * Channel Field Definitions
337 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
338 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
339 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
340 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
341 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -60
342 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -60
343 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
344 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
346 #define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127
347 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127
348 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60
349 #define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127
350 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127
351 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60
353 #define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118
776 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
777 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz…
779 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
926 * Channel 1 Register Map
939 * Channel 1 Field Definitions
990 * Channel 2 Register Map
1003 * Channel 2 Field Definitions
1062 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
1327 #define AR9300_DFS_FIRPWR -28