Lines Matching +full:0 +full:- +full:5
18 #include "hw-ops.h"
25 0, 3, 9, 15, 21, 27
37 5, 5, 4, 4, 3
42 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; in ar9003_hw_is_aic_enabled()
46 * HW code and the driver-layer support ready. in ar9003_hw_is_aic_enabled()
50 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_AIC) in ar9003_hw_is_aic_enabled()
67 for (i = index - 1; i >= 0; i--) { in ar9003_aic_find_valid()
73 if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0)) in ar9003_aic_find_valid()
74 i = -1; in ar9003_aic_find_valid()
80 * type 0: aic_lin_table, 1: com_att_db_table
84 int16_t i = -1; in ar9003_aic_find_index()
86 if (type == 0) { in ar9003_aic_find_index()
87 for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) { in ar9003_aic_find_index()
92 for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) { in ar9003_aic_find_index()
94 i--; in ar9003_aic_find_index()
100 i = -1; in ar9003_aic_find_index()
111 REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00); in ar9003_aic_gain_table()
112 REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438); in ar9003_aic_gain_table()
115 aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
116 (0x1f & 0x1f); /* -01 dB: 4'd1, 5'd31, 00 dB: 4'd0, 5'd31 */ in ar9003_aic_gain_table()
117 aic_atten_word[1] = (0x3 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
118 (0x1f & 0x1f); /* -03 dB: 4'd3, 5'd31, -02 dB: 4'd2, 5'd31 */ in ar9003_aic_gain_table()
119 aic_atten_word[2] = (0x5 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
120 (0x1f & 0x1f); /* -05 dB: 4'd5, 5'd31, -04 dB: 4'd4, 5'd31 */ in ar9003_aic_gain_table()
121 aic_atten_word[3] = (0x1 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
122 (0x1e & 0x1f); /* -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30 */ in ar9003_aic_gain_table()
123 aic_atten_word[4] = (0x3 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
124 (0x1e & 0x1f); /* -09 dB: 4'd3, 5'd30, -08 dB: 4'd2, 5'd30 */ in ar9003_aic_gain_table()
125 aic_atten_word[5] = (0x5 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
126 (0x1e & 0x1f); /* -11 dB: 4'd5, 5'd30, -10 dB: 4'd4, 5'd30 */ in ar9003_aic_gain_table()
127 aic_atten_word[6] = (0x1 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
128 (0xf & 0x1f); /* -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15 */ in ar9003_aic_gain_table()
129 aic_atten_word[7] = (0x3 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
130 (0xf & 0x1f); /* -15 dB: 4'd3, 5'd15, -14 dB: 4'd2, 5'd15 */ in ar9003_aic_gain_table()
131 aic_atten_word[8] = (0x5 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
132 (0xf & 0x1f); /* -17 dB: 4'd5, 5'd15, -16 dB: 4'd4, 5'd15 */ in ar9003_aic_gain_table()
133 aic_atten_word[9] = (0x1 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
134 (0x7 & 0x1f); /* -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07 */ in ar9003_aic_gain_table()
135 aic_atten_word[10] = (0x3 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
136 (0x7 & 0x1f); /* -21 dB: 4'd3, 5'd07, -20 dB: 4'd2, 5'd07 */ in ar9003_aic_gain_table()
137 aic_atten_word[11] = (0x5 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
138 (0x7 & 0x1f); /* -23 dB: 4'd5, 5'd07, -22 dB: 4'd4, 5'd07 */ in ar9003_aic_gain_table()
139 aic_atten_word[12] = (0x7 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x6 & 0xf) << 5 | in ar9003_aic_gain_table()
140 (0x7 & 0x1f); /* -25 dB: 4'd7, 5'd07, -24 dB: 4'd6, 5'd07 */ in ar9003_aic_gain_table()
141 aic_atten_word[13] = (0x3 & 0xf) << 14 | (0x3 & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
142 (0x3 & 0x1f); /* -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03 */ in ar9003_aic_gain_table()
143 aic_atten_word[14] = (0x5 & 0xf) << 14 | (0x3 & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
144 (0x3 & 0x1f); /* -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03 */ in ar9003_aic_gain_table()
145 aic_atten_word[15] = (0x1 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x0 & 0xf) << 5 | in ar9003_aic_gain_table()
146 (0x1 & 0x1f); /* -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01 */ in ar9003_aic_gain_table()
147 aic_atten_word[16] = (0x3 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x2 & 0xf) << 5 | in ar9003_aic_gain_table()
148 (0x1 & 0x1f); /* -33 dB: 4'd3, 5'd01, -32 dB: 4'd2, 5'd01 */ in ar9003_aic_gain_table()
149 aic_atten_word[17] = (0x5 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x4 & 0xf) << 5 | in ar9003_aic_gain_table()
150 (0x1 & 0x1f); /* -35 dB: 4'd5, 5'd01, -34 dB: 4'd4, 5'd01 */ in ar9003_aic_gain_table()
151 aic_atten_word[18] = (0x7 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x6 & 0xf) << 5 | in ar9003_aic_gain_table()
152 (0x1 & 0x1f); /* -37 dB: 4'd7, 5'd01, -36 dB: 4'd6, 5'd01 */ in ar9003_aic_gain_table()
155 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_gain_table()
159 for (i = 0; i < 19; i++) { in ar9003_aic_gain_table()
160 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), in ar9003_aic_gain_table()
167 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_cal_start()
171 REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000), in ar9003_aic_cal_start()
175 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_cal_start()
176 REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0); in ar9003_aic_cal_start()
177 aic->aic_sram[i] = 0; in ar9003_aic_cal_start()
181 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
186 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
187 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
188 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
191 (SM(0, AR_PHY_AIC_MON_ENABLE) | in ar9003_aic_cal_start()
193 SM(0, AR_PHY_AIC_CAL_ENABLE) | in ar9003_aic_cal_start()
194 SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) | in ar9003_aic_cal_start()
195 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
199 SM(0, AR_PHY_AIC_BT_IDLE_CFG) | in ar9003_aic_cal_start()
202 SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) | in ar9003_aic_cal_start()
204 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9003_aic_cal_start()
208 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9003_aic_cal_start()
215 SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) | in ar9003_aic_cal_start()
216 SM(0, AR_PHY_AIC_CAL_SYNTH_TOGGLE) | in ar9003_aic_cal_start()
217 SM(0, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) | in ar9003_aic_cal_start()
233 SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) | in ar9003_aic_cal_start()
240 SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) | in ar9003_aic_cal_start()
251 aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32); in ar9003_aic_cal_start()
258 aic->aic_caled_chan = 0; in ar9003_aic_cal_start()
259 aic->aic_cal_state = AIC_CAL_STATE_STARTED; in ar9003_aic_cal_start()
261 return aic->aic_cal_state; in ar9003_aic_cal_start()
266 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_cal_post_process()
275 memset(&cal_sram_valid, 0, sizeof(cal_sram_valid)); in ar9003_aic_cal_post_process()
276 memset(&aic_sram, 0, sizeof(aic_sram)); in ar9003_aic_cal_post_process()
278 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_cal_post_process()
280 value = aic->aic_sram[i]; in ar9003_aic_cal_post_process()
301 dir_path_sign = (sram.vga_dir_sign) ? 1 : -1; in ar9003_aic_cal_post_process()
302 quad_path_sign = (sram.vga_quad_sign) ? 1 : -1; in ar9003_aic_cal_post_process()
311 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_cal_post_process()
317 start_idx = ar9003_aic_find_valid(cal_sram_valid, 0, i); in ar9003_aic_cal_post_process()
320 if (start_idx < 0) { in ar9003_aic_cal_post_process()
325 if (end_idx < 0) { in ar9003_aic_cal_post_process()
331 ((aic_sram[start_idx].dir_path_gain_lin - in ar9003_aic_cal_post_process()
333 (start_idx - i) + ((end_idx - i) >> 1)) / in ar9003_aic_cal_post_process()
334 (end_idx - i) + in ar9003_aic_cal_post_process()
337 ((aic_sram[start_idx].quad_path_gain_lin - in ar9003_aic_cal_post_process()
339 (start_idx - i) + ((end_idx - i) >> 1)) / in ar9003_aic_cal_post_process()
340 (end_idx - i) + in ar9003_aic_cal_post_process()
344 if (end_idx < 0) { in ar9003_aic_cal_post_process()
346 end_idx = ar9003_aic_find_valid(cal_sram_valid, 0, start_idx); in ar9003_aic_cal_post_process()
348 if (end_idx < 0) { in ar9003_aic_cal_post_process()
354 ((aic_sram[start_idx].dir_path_gain_lin - in ar9003_aic_cal_post_process()
356 (i - start_idx) + ((start_idx - end_idx) >> 1)) / in ar9003_aic_cal_post_process()
357 (start_idx - end_idx) + in ar9003_aic_cal_post_process()
360 ((aic_sram[start_idx].quad_path_gain_lin - in ar9003_aic_cal_post_process()
362 (i - start_idx) + ((start_idx - end_idx) >> 1)) / in ar9003_aic_cal_post_process()
363 (start_idx - end_idx) + in ar9003_aic_cal_post_process()
366 } else if (start_idx >= 0){ in ar9003_aic_cal_post_process()
369 (((end_idx - i) * aic_sram[start_idx].dir_path_gain_lin) + in ar9003_aic_cal_post_process()
370 ((i - start_idx) * aic_sram[end_idx].dir_path_gain_lin) + in ar9003_aic_cal_post_process()
371 ((end_idx - start_idx) >> 1)) / in ar9003_aic_cal_post_process()
372 (end_idx - start_idx); in ar9003_aic_cal_post_process()
374 (((end_idx - i) * aic_sram[start_idx].quad_path_gain_lin) + in ar9003_aic_cal_post_process()
375 ((i - start_idx) * aic_sram[end_idx].quad_path_gain_lin) + in ar9003_aic_cal_post_process()
376 ((end_idx - start_idx) >> 1))/ in ar9003_aic_cal_post_process()
377 (end_idx - start_idx); in ar9003_aic_cal_post_process()
382 i = ar9003_aic_find_valid(cal_sram_valid, 1, 0); in ar9003_aic_cal_post_process()
383 if (i < 0) { in ar9003_aic_cal_post_process()
384 i = 0; in ar9003_aic_cal_post_process()
387 fixed_com_att_db = com_att_db_table[MS(aic->aic_sram[i], in ar9003_aic_cal_post_process()
390 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_cal_post_process()
395 (aic_sram[i].dir_path_gain_lin >= 0) ? 1 : 0; in ar9003_aic_cal_post_process()
397 (aic_sram[i].quad_path_gain_lin >= 0) ? 1 : 0; in ar9003_aic_cal_post_process()
400 ar9003_aic_find_index(0, abs(aic_sram[i].dir_path_gain_lin)) - in ar9003_aic_cal_post_process()
403 ar9003_aic_find_index(0, abs(aic_sram[i].quad_path_gain_lin)) - in ar9003_aic_cal_post_process()
420 aic->aic_sram[i] = (SM(sram.vga_dir_sign, in ar9003_aic_cal_post_process()
439 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_cal_done()
447 aic->aic_cal_state = AIC_CAL_STATE_DONE; in ar9003_aic_cal_done()
449 aic->aic_cal_state = AIC_CAL_STATE_ERROR; in ar9003_aic_cal_done()
455 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; in ar9003_aic_cal_continue()
456 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_cal_continue()
459 num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN); in ar9003_aic_cal_continue()
462 aic->aic_cal_state = AIC_CAL_STATE_ERROR; in ar9003_aic_cal_continue()
463 return aic->aic_cal_state; in ar9003_aic_cal_continue()
467 for (i = 0; i < 10000; i++) { in ar9003_aic_cal_continue()
469 AR_PHY_AIC_CAL_ENABLE) == 0) in ar9003_aic_cal_continue()
481 AR_PHY_AIC_CAL_ENABLE) != 0) { in ar9003_aic_cal_continue()
489 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_cal_continue()
494 if (value & 0x01) { in ar9003_aic_cal_continue()
495 if (aic->aic_sram[i] == 0) in ar9003_aic_cal_continue()
496 aic->aic_caled_chan++; in ar9003_aic_cal_continue()
498 aic->aic_sram[i] = value; in ar9003_aic_cal_continue()
505 if ((aic->aic_caled_chan >= num_chan) || cal_once) { in ar9003_aic_cal_continue()
515 return aic->aic_cal_state; in ar9003_aic_cal_continue()
521 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_calibration()
524 switch (aic->aic_cal_state) { in ar9003_aic_calibration()
543 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_start_normal()
546 if (aic->aic_cal_state != AIC_CAL_STATE_DONE) in ar9003_aic_start_normal()
553 for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { in ar9003_aic_start_normal()
554 REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]); in ar9003_aic_start_normal()
558 REG_WRITE(ah, 0xa6b0, 0x80); in ar9003_aic_start_normal()
559 REG_WRITE(ah, 0xa6b4, 0x5b2df0); in ar9003_aic_start_normal()
560 REG_WRITE(ah, 0xa6b8, 0x10762cc8); in ar9003_aic_start_normal()
561 REG_WRITE(ah, 0xa6bc, 0x1219a4b); in ar9003_aic_start_normal()
562 REG_WRITE(ah, 0xa6c0, 0x1e01); in ar9003_aic_start_normal()
563 REG_WRITE(ah, 0xb6b4, 0xf0); in ar9003_aic_start_normal()
564 REG_WRITE(ah, 0xb6c0, 0x1e01); in ar9003_aic_start_normal()
565 REG_WRITE(ah, 0xb6b0, 0x81); in ar9003_aic_start_normal()
566 REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000); in ar9003_aic_start_normal()
568 aic->aic_enabled = true; in ar9003_aic_start_normal()
570 return 0; in ar9003_aic_start_normal()
575 struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; in ar9003_aic_cal_reset()
577 aic->aic_cal_state = AIC_CAL_STATE_IDLE; in ar9003_aic_cal_reset()
578 return aic->aic_cal_state; in ar9003_aic_cal_reset()
583 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; in ar9003_aic_calibration_single()
587 num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN); in ar9003_aic_calibration_single()
599 priv_ops->is_aic_enabled = ar9003_hw_is_aic_enabled; in ar9003_hw_attach_aic_ops()