Lines Matching refs:queue
63 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_num_tx_pending() argument
66 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_num_tx_pending()
69 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_num_tx_pending()
76 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue)); in ath5k_hw_num_tx_pending()
82 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_num_tx_pending()
94 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_release_tx_queue() argument
96 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) in ath5k_hw_release_tx_queue()
100 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; in ath5k_hw_release_tx_queue()
102 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); in ath5k_hw_release_tx_queue()
138 ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, in ath5k_hw_get_tx_queueprops() argument
141 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info)); in ath5k_hw_get_tx_queueprops()
154 ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, in ath5k_hw_set_tx_queueprops() argument
159 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_set_tx_queueprops()
161 qi = &ah->ah_txq[queue]; in ath5k_hw_set_tx_queueprops()
206 unsigned int queue; in ath5k_hw_setup_tx_queue() local
216 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA; in ath5k_hw_setup_tx_queue()
220 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON; in ath5k_hw_setup_tx_queue()
228 queue = queue_info->tqi_subtype; in ath5k_hw_setup_tx_queue()
231 queue = AR5K_TX_QUEUE_ID_UAPSD; in ath5k_hw_setup_tx_queue()
234 queue = AR5K_TX_QUEUE_ID_BEACON; in ath5k_hw_setup_tx_queue()
237 queue = AR5K_TX_QUEUE_ID_CAB; in ath5k_hw_setup_tx_queue()
247 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info)); in ath5k_hw_setup_tx_queue()
248 ah->ah_txq[queue].tqi_type = queue_type; in ath5k_hw_setup_tx_queue()
252 ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info); in ath5k_hw_setup_tx_queue()
262 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue); in ath5k_hw_setup_tx_queue()
264 return queue; in ath5k_hw_setup_tx_queue()
282 unsigned int queue) in ath5k_hw_set_tx_retry_limits() argument
286 struct ath5k_txq_info *tq = &ah->ah_txq[queue]; in ath5k_hw_set_tx_retry_limits()
288 if (queue > 0) in ath5k_hw_set_tx_retry_limits()
311 AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); in ath5k_hw_set_tx_retry_limits()
324 ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_reset_tx_queue() argument
326 struct ath5k_txq_info *tq = &ah->ah_txq[queue]; in ath5k_hw_reset_tx_queue()
328 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_reset_tx_queue()
344 AR5K_QUEUE_DFS_LOCAL_IFS(queue)); in ath5k_hw_reset_tx_queue()
349 ath5k_hw_set_tx_retry_limits(ah, queue); in ath5k_hw_reset_tx_queue()
357 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), in ath5k_hw_reset_tx_queue()
362 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), in ath5k_hw_reset_tx_queue()
371 AR5K_QUEUE_CBRCFG(queue)); in ath5k_hw_reset_tx_queue()
373 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
377 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
386 AR5K_QUEUE_RDYTIMECFG(queue)); in ath5k_hw_reset_tx_queue()
392 AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); in ath5k_hw_reset_tx_queue()
395 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
402 AR5K_QUEUE_DFS_MISC(queue)); in ath5k_hw_reset_tx_queue()
407 AR5K_QUEUE_DFS_MISC(queue)); in ath5k_hw_reset_tx_queue()
414 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
419 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), in ath5k_hw_reset_tx_queue()
429 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
439 AR5K_QUEUE_RDYTIMECFG(queue)); in ath5k_hw_reset_tx_queue()
441 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), in ath5k_hw_reset_tx_queue()
447 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), in ath5k_hw_reset_tx_queue()
463 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue); in ath5k_hw_reset_tx_queue()
466 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue); in ath5k_hw_reset_tx_queue()
469 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue); in ath5k_hw_reset_tx_queue()
472 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue); in ath5k_hw_reset_tx_queue()
475 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue); in ath5k_hw_reset_tx_queue()
478 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue); in ath5k_hw_reset_tx_queue()
481 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue); in ath5k_hw_reset_tx_queue()
484 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue); in ath5k_hw_reset_tx_queue()
487 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue); in ath5k_hw_reset_tx_queue()
539 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue); in ath5k_hw_reset_tx_queue()