Lines Matching refs:mode
41 unsigned int mode) in ath5k_eeprom_bin2freq() argument
48 if (mode == AR5K_EEPROM_MODE_11A) { in ath5k_eeprom_bin2freq()
190 unsigned int mode) in ath5k_eeprom_read_ants() argument
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_ants()
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
205 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; in ath5k_eeprom_read_ants()
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; in ath5k_eeprom_read_ants()
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; in ath5k_eeprom_read_ants()
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; in ath5k_eeprom_read_ants()
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; in ath5k_eeprom_read_ants()
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
221 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
224 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = in ath5k_eeprom_read_ants()
225 (ee->ee_ant_control[mode][0] << 4); in ath5k_eeprom_read_ants()
226 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = in ath5k_eeprom_read_ants()
227 ee->ee_ant_control[mode][1] | in ath5k_eeprom_read_ants()
228 (ee->ee_ant_control[mode][2] << 6) | in ath5k_eeprom_read_ants()
229 (ee->ee_ant_control[mode][3] << 12) | in ath5k_eeprom_read_ants()
230 (ee->ee_ant_control[mode][4] << 18) | in ath5k_eeprom_read_ants()
231 (ee->ee_ant_control[mode][5] << 24); in ath5k_eeprom_read_ants()
232 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = in ath5k_eeprom_read_ants()
233 ee->ee_ant_control[mode][6] | in ath5k_eeprom_read_ants()
234 (ee->ee_ant_control[mode][7] << 6) | in ath5k_eeprom_read_ants()
235 (ee->ee_ant_control[mode][8] << 12) | in ath5k_eeprom_read_ants()
236 (ee->ee_ant_control[mode][9] << 18) | in ath5k_eeprom_read_ants()
237 (ee->ee_ant_control[mode][10] << 24); in ath5k_eeprom_read_ants()
250 unsigned int mode) in ath5k_eeprom_read_modes() argument
256 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_modes()
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); in ath5k_eeprom_read_modes()
259 switch (mode) { in ath5k_eeprom_read_modes()
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7; in ath5k_eeprom_read_modes()
262 ee->ee_db[mode][3] = (val >> 2) & 0x7; in ath5k_eeprom_read_modes()
263 ee->ee_ob[mode][2] = (val << 1) & 0x7; in ath5k_eeprom_read_modes()
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; in ath5k_eeprom_read_modes()
267 ee->ee_db[mode][2] = (val >> 12) & 0x7; in ath5k_eeprom_read_modes()
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7; in ath5k_eeprom_read_modes()
269 ee->ee_db[mode][1] = (val >> 6) & 0x7; in ath5k_eeprom_read_modes()
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
271 ee->ee_db[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7; in ath5k_eeprom_read_modes()
276 ee->ee_db[mode][1] = val & 0x7; in ath5k_eeprom_read_modes()
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
282 ee->ee_thr_62[mode] = val & 0xff; in ath5k_eeprom_read_modes()
285 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; in ath5k_eeprom_read_modes()
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; in ath5k_eeprom_read_modes()
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); in ath5k_eeprom_read_modes()
297 ee->ee_noise_floor_thr[mode] = val & 0xff; in ath5k_eeprom_read_modes()
300 ee->ee_noise_floor_thr[mode] = in ath5k_eeprom_read_modes()
301 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; in ath5k_eeprom_read_modes()
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; in ath5k_eeprom_read_modes()
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf; in ath5k_eeprom_read_modes()
306 ee->ee_xpd[mode] = val & 0x1; in ath5k_eeprom_read_modes()
309 mode != AR5K_EEPROM_MODE_11B) in ath5k_eeprom_read_modes()
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; in ath5k_eeprom_read_modes()
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
316 if (mode == AR5K_EEPROM_MODE_11A) in ath5k_eeprom_read_modes()
317 ee->ee_xr_power[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
320 ee->ee_ob[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
321 ee->ee_db[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
326 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; in ath5k_eeprom_read_modes()
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38; in ath5k_eeprom_read_modes()
334 if (mode == AR5K_EEPROM_MODE_11G) { in ath5k_eeprom_read_modes()
342 mode == AR5K_EEPROM_MODE_11A) { in ath5k_eeprom_read_modes()
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; in ath5k_eeprom_read_modes()
353 switch (mode) { in ath5k_eeprom_read_modes()
359 ee->ee_margin_tx_rx[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
365 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
367 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
370 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_modes()
372 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
376 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
378 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
387 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
389 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
392 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_modes()
394 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
397 ee->ee_turbo_max_power[mode] = val & 0x7f; in ath5k_eeprom_read_modes()
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; in ath5k_eeprom_read_modes()
402 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
404 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
411 ee->ee_q_cal[mode] = val & 0x1f; in ath5k_eeprom_read_modes()
426 switch (mode) { in ath5k_eeprom_read_modes()
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; in ath5k_eeprom_read_modes()
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; in ath5k_eeprom_read_modes()
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; in ath5k_eeprom_read_modes()
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; in ath5k_eeprom_read_modes()
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; in ath5k_eeprom_read_modes()
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_modes()
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; in ath5k_eeprom_read_modes()
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; in ath5k_eeprom_read_modes()
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; in ath5k_eeprom_read_modes()
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; in ath5k_eeprom_read_modes()
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; in ath5k_eeprom_read_modes()
471 unsigned int mode; in ath5k_eeprom_init_modes() local
485 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) { in ath5k_eeprom_init_modes()
486 offset = mode_offset[mode]; in ath5k_eeprom_init_modes()
488 ret = ath5k_eeprom_read_ants(ah, &offset, mode); in ath5k_eeprom_init_modes()
492 ret = ath5k_eeprom_read_modes(ah, &offset, mode); in ath5k_eeprom_init_modes()
511 struct ath5k_chan_pcal_info *pc, unsigned int mode) in ath5k_eeprom_read_freq_list() argument
519 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_freq_list()
528 freq1, mode); in ath5k_eeprom_read_freq_list()
529 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
536 freq2, mode); in ath5k_eeprom_read_freq_list()
537 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
601 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset) in ath5k_eeprom_init_11bg_2413() argument
606 switch (mode) { in ath5k_eeprom_init_11bg_2413()
619 mode); in ath5k_eeprom_init_11bg_2413()
667 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode) in ath5k_eeprom_free_pcal_info() argument
673 switch (mode) { in ath5k_eeprom_free_pcal_info()
693 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_free_pcal_info()
714 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode, in ath5k_eeprom_convert_pcal_info_5111() argument
721 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5111()
724 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5111()
743 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) { in ath5k_eeprom_convert_pcal_info_5111()
752 ee->ee_pd_gains[mode] = 1; in ath5k_eeprom_convert_pcal_info_5111()
790 ath5k_eeprom_free_pcal_info(ah, mode); in ath5k_eeprom_convert_pcal_info_5111()
796 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode) in ath5k_eeprom_read_pcal_info_5111() argument
805 switch (mode) { in ath5k_eeprom_read_pcal_info_5111()
830 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
843 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
849 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5111()
883 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal); in ath5k_eeprom_read_pcal_info_5111()
905 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode, in ath5k_eeprom_convert_pcal_info_5112() argument
910 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5112()
914 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5112()
928 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_5112()
1013 ath5k_eeprom_free_pcal_info(ah, mode); in ath5k_eeprom_convert_pcal_info_5112()
1019 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode) in ath5k_eeprom_read_pcal_info_5112() argument
1024 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_5112()
1037 if ((ee->ee_x_gain[mode] >> i) & 0x1) in ath5k_eeprom_read_pcal_info_5112()
1040 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_5112()
1045 switch (mode) { in ath5k_eeprom_read_pcal_info_5112()
1078 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5112()
1127 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info); in ath5k_eeprom_read_pcal_info_5112()
1154 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode) in ath5k_pdgains_size_2413() argument
1159 sz = pdgains_size[ee->ee_pd_gains[mode] - 1]; in ath5k_pdgains_size_2413()
1160 sz *= ee->ee_n_piers[mode]; in ath5k_pdgains_size_2413()
1168 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode) in ath5k_cal_data_offset_2413() argument
1172 switch (mode) { in ath5k_cal_data_offset_2413()
1197 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode, in ath5k_eeprom_convert_pcal_info_2413() argument
1202 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_2413()
1206 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_2413()
1220 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_2413()
1228 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1267 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1276 ath5k_eeprom_free_pcal_info(ah, mode); in ath5k_eeprom_convert_pcal_info_2413()
1282 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode) in ath5k_eeprom_read_pcal_info_2413() argument
1287 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_2413()
1300 if ((ee->ee_x_gain[mode] >> idx) & 0x1) in ath5k_eeprom_read_pcal_info_2413()
1304 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_2413()
1309 offset = ath5k_cal_data_offset_2413(ee, mode); in ath5k_eeprom_read_pcal_info_2413()
1310 switch (mode) { in ath5k_eeprom_read_pcal_info_2413()
1323 ath5k_eeprom_init_11bg_2413(ah, mode, offset); in ath5k_eeprom_read_pcal_info_2413()
1331 ath5k_eeprom_init_11bg_2413(ah, mode, offset); in ath5k_eeprom_read_pcal_info_2413()
1339 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_2413()
1461 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo); in ath5k_eeprom_read_pcal_info_2413()
1473 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode) in ath5k_eeprom_read_target_rate_pwr_info() argument
1483 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode]; in ath5k_eeprom_read_target_rate_pwr_info()
1484 switch (mode) { in ath5k_eeprom_read_target_rate_pwr_info()
1488 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1493 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */ in ath5k_eeprom_read_target_rate_pwr_info()
1498 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1509 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); in ath5k_eeprom_read_target_rate_pwr_info()
1530 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_target_rate_pwr_info()
1571 int (*read_pcal)(struct ath5k_hw *hw, int mode); in ath5k_eeprom_read_pcal_info()
1572 int mode; in ath5k_eeprom_read_pcal_info() local
1585 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; in ath5k_eeprom_read_pcal_info()
1586 mode++) { in ath5k_eeprom_read_pcal_info()
1587 err = read_pcal(ah, mode); in ath5k_eeprom_read_pcal_info()
1591 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode); in ath5k_eeprom_read_pcal_info()
1778 u8 mode; in ath5k_eeprom_detach() local
1780 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) in ath5k_eeprom_detach()
1781 ath5k_eeprom_free_pcal_info(ah, mode); in ath5k_eeprom_detach()