ath/ath5k/desc.h

2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
24  * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
38  * struct ath5k_hw_rx_status - Common hardware RX status descriptor
71 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S		9
97 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S		9
105  * enum ath5k_phy_error_code - PHY Error codes
151  * struct ath5k_hw_2w_tx_ctl  - 5210/5211 hardware 2-word TX control descriptor
168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211		0x00800000 /* [5211] virtual end-of-list */
173 		(ah->ah_version == AR5K_AR5210 ?		\
188 			(ah->ah_version == AR5K_AR5210 ?		\
207  * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
225 #define AR5K_4W_TX_DESC_CTL0_VEOL		0x00800000 /* virtual end-of-list */
251 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0	0x000f0000 /* series 0 max attempts */
253 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1	0x00f00000 /* series 1 max attempts */
255 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2	0x0f000000 /* series 2 max attempts */
257 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3	0xf0000000 /* series 3 max attempts */
261 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0		0x0000001f /* series 0 tx rate */
262 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1		0x000003e0 /* series 1 tx rate */
264 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2		0x00007c00 /* series 2 tx rate */
266 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3		0x000f8000 /* series 3 tx rate */
272  * struct ath5k_hw_tx_status - Common TX status descriptor
306 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212	0x00600000 /* [5212] final TX attempt series ix */
312  * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
322  * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
332  * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
342  * struct ath5k_desc - Atheros hardware DMA descriptor