35 	struct ath5k_capabilities *caps = &ah->ah_capabilities;  in ath5k_hw_set_capabilities()  local
39 	ee_header = caps->cap_eeprom.ee_header;  in ath5k_hw_set_capabilities()
46 		caps->cap_range.range_5ghz_min = 5120;  in ath5k_hw_set_capabilities()
47 		caps->cap_range.range_5ghz_max = 5430;  in ath5k_hw_set_capabilities()
48 		caps->cap_range.range_2ghz_min = 0;  in ath5k_hw_set_capabilities()
49 		caps->cap_range.range_2ghz_max = 0;  in ath5k_hw_set_capabilities()
52 		__set_bit(AR5K_MODE_11A, caps->cap_mode);  in ath5k_hw_set_capabilities()
69 			if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain))  in ath5k_hw_set_capabilities()
70 				caps->cap_range.range_5ghz_min = 4920;  in ath5k_hw_set_capabilities()
72 				caps->cap_range.range_5ghz_min = 5005;  in ath5k_hw_set_capabilities()
73 			caps->cap_range.range_5ghz_max = 6100;  in ath5k_hw_set_capabilities()
76 			__set_bit(AR5K_MODE_11A, caps->cap_mode);  in ath5k_hw_set_capabilities()
85 			caps->cap_range.range_2ghz_min = 2412;  in ath5k_hw_set_capabilities()
86 			caps->cap_range.range_2ghz_max = 2732;  in ath5k_hw_set_capabilities()
91 			if (!caps->cap_needs_2GHz_ovr) {  in ath5k_hw_set_capabilities()
94 							caps->cap_mode);  in ath5k_hw_set_capabilities()
99 							caps->cap_mode);  in ath5k_hw_set_capabilities()
105 		__clear_bit(AR5K_MODE_11A, caps->cap_mode);  in ath5k_hw_set_capabilities()
109 		caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;  in ath5k_hw_set_capabilities()
111 		caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;  in ath5k_hw_set_capabilities()
115 		caps->cap_has_phyerr_counters = true;  in ath5k_hw_set_capabilities()
117 		caps->cap_has_phyerr_counters = false;  in ath5k_hw_set_capabilities()
121 		caps->cap_has_mrr_support = true;  in ath5k_hw_set_capabilities()
123 		caps->cap_has_mrr_support = false;  in ath5k_hw_set_capabilities()