Lines Matching +full:reo2host +full:- +full:destination +full:- +full:ring3
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
35 * 4K - 32 = 0xFE0
65 "mhi-er0",
66 "mhi-er1",
83 "host2wbm-desc-feed",
84 "host2reo-re-injection",
85 "host2reo-command",
86 "host2rxdma-monitor-ring3",
87 "host2rxdma-monitor-ring2",
88 "host2rxdma-monitor-ring1",
89 "reo2ost-exception",
90 "wbm2host-rx-release",
91 "reo2host-status",
92 "reo2host-destination-ring4",
93 "reo2host-destination-ring3",
94 "reo2host-destination-ring2",
95 "reo2host-destination-ring1",
96 "rxdma2host-monitor-destination-mac3",
97 "rxdma2host-monitor-destination-mac2",
98 "rxdma2host-monitor-destination-mac1",
99 "ppdu-end-interrupts-mac3",
100 "ppdu-end-interrupts-mac2",
101 "ppdu-end-interrupts-mac1",
102 "rxdma2host-monitor-status-ring-mac3",
103 "rxdma2host-monitor-status-ring-mac2",
104 "rxdma2host-monitor-status-ring-mac1",
105 "host2rxdma-host-buf-ring-mac3",
106 "host2rxdma-host-buf-ring-mac2",
107 "host2rxdma-host-buf-ring-mac1",
108 "rxdma2host-destination-ring-mac3",
109 "rxdma2host-destination-ring-mac2",
110 "rxdma2host-destination-ring-mac1",
111 "host2tcl-input-ring4",
112 "host2tcl-input-ring3",
113 "host2tcl-input-ring2",
114 "host2tcl-input-ring1",
115 "wbm2host-tx-completions-ring4",
116 "wbm2host-tx-completions-ring3",
117 "wbm2host-tx-completions-ring2",
118 "wbm2host-tx-completions-ring1",
119 "tcl2host-status-ring",
126 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_wake_up()
133 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_release()
148 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_select_window()
153 lockdep_assert_held(&ab_pci->window_lock); in ath12k_pci_select_window()
156 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; in ath12k_pci_select_window()
159 if (window != ab_pci->register_window) { in ath12k_pci_select_window()
161 ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
162 ioread32(ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
163 ab_pci->register_window = window; in ath12k_pci_select_window()
175 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
176 ab_pci->register_window = window; in ath12k_pci_select_static_window()
177 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
179 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_static_window()
333 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_free_ext_irq()
335 for (j = 0; j < irq_grp->num_irq; j++) in ath12k_pci_free_ext_irq()
336 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); in ath12k_pci_free_ext_irq()
338 netif_napi_del(&irq_grp->napi); in ath12k_pci_free_ext_irq()
346 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_free_irq()
350 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); in ath12k_pci_free_irq()
361 enable_irq(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_enable()
369 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_disable()
376 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ce_irqs_disable()
378 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_disable()
390 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_sync_ce_irqs()
395 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ce_irqs()
403 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_tasklet()
405 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_tasklet()
411 struct ath12k_base *ab = ce_pipe->ab; in ath12k_pci_ce_interrupt_handler()
413 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) in ath12k_pci_ce_interrupt_handler()
417 ce_pipe->timestamp = jiffies; in ath12k_pci_ce_interrupt_handler()
419 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_interrupt_handler()
420 tasklet_schedule(&ce_pipe->intr_tq); in ath12k_pci_ce_interrupt_handler()
429 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_disable()
430 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_disable()
437 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) in __ath12k_pci_ext_irq_disable()
441 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in __ath12k_pci_ext_irq_disable()
445 napi_synchronize(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
446 napi_disable(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
454 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_enable()
455 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_enable()
463 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_sync_ext_irqs()
465 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_sync_ext_irqs()
466 irq_idx = irq_grp->irqs[j]; in ath12k_pci_sync_ext_irqs()
467 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ext_irqs()
477 struct ath12k_base *ab = irq_grp->ab; in ath12k_pci_ext_grp_napi_poll()
495 struct ath12k_base *ab = irq_grp->ab; in ath12k_pci_ext_interrupt_handler()
497 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) in ath12k_pci_ext_interrupt_handler()
500 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); in ath12k_pci_ext_interrupt_handler()
503 irq_grp->timestamp = jiffies; in ath12k_pci_ext_interrupt_handler()
507 napi_schedule(&irq_grp->napi); in ath12k_pci_ext_interrupt_handler()
526 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_config()
529 irq_grp->ab = ab; in ath12k_pci_ext_irq_config()
530 irq_grp->grp_id = i; in ath12k_pci_ext_irq_config()
531 init_dummy_netdev(&irq_grp->napi_ndev); in ath12k_pci_ext_irq_config()
532 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, in ath12k_pci_ext_irq_config()
535 if (ab->hw_params->ring_mask->tx[i] || in ath12k_pci_ext_irq_config()
536 ab->hw_params->ring_mask->rx[i] || in ath12k_pci_ext_irq_config()
537 ab->hw_params->ring_mask->rx_err[i] || in ath12k_pci_ext_irq_config()
538 ab->hw_params->ring_mask->rx_wbm_rel[i] || in ath12k_pci_ext_irq_config()
539 ab->hw_params->ring_mask->reo_status[i] || in ath12k_pci_ext_irq_config()
540 ab->hw_params->ring_mask->host2rxdma[i] || in ath12k_pci_ext_irq_config()
541 ab->hw_params->ring_mask->rx_mon_dest[i]) { in ath12k_pci_ext_irq_config()
545 irq_grp->num_irq = num_irq; in ath12k_pci_ext_irq_config()
546 irq_grp->irqs[0] = base_idx + i; in ath12k_pci_ext_irq_config()
548 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_ext_irq_config()
549 int irq_idx = irq_grp->irqs[j]; in ath12k_pci_ext_irq_config()
551 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); in ath12k_pci_ext_irq_config()
553 ab->irq_num[irq_idx] = irq; in ath12k_pci_ext_irq_config()
568 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ext_irq_config()
592 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_config_irq()
597 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); in ath12k_pci_config_irq()
598 ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_config_irq()
602 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); in ath12k_pci_config_irq()
613 ab->irq_num[irq_idx] = irq; in ath12k_pci_config_irq()
628 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; in ath12k_pci_init_qmi_ce_config()
630 cfg->tgt_ce = ab->hw_params->target_ce_config; in ath12k_pci_init_qmi_ce_config()
631 cfg->tgt_ce_len = ab->hw_params->target_ce_count; in ath12k_pci_init_qmi_ce_config()
633 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; in ath12k_pci_init_qmi_ce_config()
634 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; in ath12k_pci_init_qmi_ce_config()
635 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; in ath12k_pci_init_qmi_ce_config()
642 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ce_irqs_enable()
644 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_enable()
653 struct pci_dev *dev = ab_pci->pdev; in ath12k_pci_msi_config()
656 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); in ath12k_pci_msi_config()
663 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); in ath12k_pci_msi_config()
678 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_msi_alloc()
679 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_msi_alloc()
684 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, in ath12k_pci_msi_alloc()
685 msi_config->total_vectors, in ath12k_pci_msi_alloc()
686 msi_config->total_vectors, in ath12k_pci_msi_alloc()
688 if (num_vectors != msi_config->total_vectors) { in ath12k_pci_msi_alloc()
690 msi_config->total_vectors, num_vectors); in ath12k_pci_msi_alloc()
693 return -EINVAL; in ath12k_pci_msi_alloc()
700 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); in ath12k_pci_msi_alloc()
703 ret = -EINVAL; in ath12k_pci_msi_alloc()
707 ab_pci->msi_ep_base_data = msi_desc->msg.data; in ath12k_pci_msi_alloc()
708 if (msi_desc->pci.msi_attrib.is_64) in ath12k_pci_msi_alloc()
709 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); in ath12k_pci_msi_alloc()
711 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); in ath12k_pci_msi_alloc()
716 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_alloc()
723 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_free()
728 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_claim()
733 if (device_id != ab_pci->dev_id) { in ath12k_pci_claim()
735 device_id, ab_pci->dev_id); in ath12k_pci_claim()
736 ret = -EIO; in ath12k_pci_claim()
758 ret = dma_set_mask_and_coherent(&pdev->dev, in ath12k_pci_claim()
768 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); in ath12k_pci_claim()
769 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); in ath12k_pci_claim()
770 if (!ab->mem) { in ath12k_pci_claim()
772 ret = -EIO; in ath12k_pci_claim()
776 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); in ath12k_pci_claim()
789 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_free_region()
790 struct pci_dev *pci_dev = ab_pci->pdev; in ath12k_pci_free_region()
792 pci_iounmap(pci_dev, ab->mem); in ath12k_pci_free_region()
793 ab->mem = NULL; in ath12k_pci_free_region()
801 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_aspm_disable()
803 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
804 &ab_pci->link_ctl); in ath12k_pci_aspm_disable()
807 ab_pci->link_ctl, in ath12k_pci_aspm_disable()
808 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), in ath12k_pci_aspm_disable()
809 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); in ath12k_pci_aspm_disable()
812 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
815 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); in ath12k_pci_aspm_disable()
820 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) in ath12k_pci_aspm_restore()
821 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_restore()
823 ab_pci->link_ctl & in ath12k_pci_aspm_restore()
831 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_kill_tasklets()
832 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_kill_tasklets()
837 tasklet_kill(&ce_pipe->intr_tq); in ath12k_pci_kill_tasklets()
855 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { in ath12k_pci_map_service_to_pipe()
856 entry = &ab->hw_params->svc_to_ce_map[i]; in ath12k_pci_map_service_to_pipe()
858 if (__le32_to_cpu(entry->service_id) != service_id) in ath12k_pci_map_service_to_pipe()
861 switch (__le32_to_cpu(entry->pipedir)) { in ath12k_pci_map_service_to_pipe()
866 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
871 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
877 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
878 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
886 return -ENOENT; in ath12k_pci_map_service_to_pipe()
903 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_get_user_msi_assignment()
906 for (idx = 0; idx < msi_config->total_users; idx++) { in ath12k_pci_get_user_msi_assignment()
907 if (strcmp(user_name, msi_config->users[idx].name) == 0) { in ath12k_pci_get_user_msi_assignment()
908 *num_vectors = msi_config->users[idx].num_vectors; in ath12k_pci_get_user_msi_assignment()
909 *user_base_data = msi_config->users[idx].base_vector in ath12k_pci_get_user_msi_assignment()
910 + ab_pci->msi_ep_base_data; in ath12k_pci_get_user_msi_assignment()
911 *base_vector = msi_config->users[idx].base_vector; in ath12k_pci_get_user_msi_assignment()
923 return -EINVAL; in ath12k_pci_get_user_msi_assignment()
930 struct pci_dev *pci_dev = to_pci_dev(ab->dev); in ath12k_pci_get_msi_address()
932 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, in ath12k_pci_get_msi_address()
935 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { in ath12k_pci_get_msi_address()
936 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, in ath12k_pci_get_msi_address()
948 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_get_ce_msi_idx()
974 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in ath12k_pci_ext_irq_enable()
977 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_enable()
979 napi_enable(&irq_grp->napi); in ath12k_pci_ext_irq_enable()
1018 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_start()
1034 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_read32()
1037 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1038 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_read32()
1039 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_read32()
1042 val = ioread32(ab->mem + offset); in ath12k_pci_read32()
1044 if (ab->static_window_map) in ath12k_pci_read32()
1050 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1052 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1054 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1059 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_read32()
1061 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1066 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1067 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_read32()
1069 ab_pci->pci_ops->release(ab); in ath12k_pci_read32()
1079 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_write32()
1082 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1083 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_write32()
1084 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_write32()
1087 iowrite32(value, ab->mem + offset); in ath12k_pci_write32()
1089 if (ab->static_window_map) in ath12k_pci_write32()
1095 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1097 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1099 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1104 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_write32()
1106 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1111 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1112 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_write32()
1114 ab_pci->pci_ops->release(ab); in ath12k_pci_write32()
1122 ab_pci->register_window = 0; in ath12k_pci_power_up()
1123 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_up()
1124 ath12k_pci_sw_reset(ab_pci->ab, true); in ath12k_pci_power_up()
1139 if (ab->static_window_map) in ath12k_pci_power_up()
1152 ath12k_pci_force_wake(ab_pci->ab); in ath12k_pci_power_down()
1155 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_down()
1156 ath12k_pci_sw_reset(ab_pci->ab, false); in ath12k_pci_power_down()
1202 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); in ath12k_pci_probe()
1204 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); in ath12k_pci_probe()
1205 return -ENOMEM; in ath12k_pci_probe()
1208 ab->dev = &pdev->dev; in ath12k_pci_probe()
1211 ab_pci->dev_id = pci_dev->device; in ath12k_pci_probe()
1212 ab_pci->ab = ab; in ath12k_pci_probe()
1213 ab_pci->pdev = pdev; in ath12k_pci_probe()
1214 ab->hif.ops = &ath12k_pci_hif_ops; in ath12k_pci_probe()
1216 spin_lock_init(&ab_pci->window_lock); in ath12k_pci_probe()
1224 switch (pci_dev->device) { in ath12k_pci_probe()
1226 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1227 ab->static_window_map = true; in ath12k_pci_probe()
1228 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; in ath12k_pci_probe()
1233 ab->hw_rev = ATH12K_HW_QCN9274_HW20; in ath12k_pci_probe()
1236 ab->hw_rev = ATH12K_HW_QCN9274_HW10; in ath12k_pci_probe()
1239 dev_err(&pdev->dev, in ath12k_pci_probe()
1242 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1247 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1248 ab->static_window_map = false; in ath12k_pci_probe()
1249 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; in ath12k_pci_probe()
1254 ab->hw_rev = ATH12K_HW_WCN7850_HW20; in ath12k_pci_probe()
1257 dev_err(&pdev->dev, in ath12k_pci_probe()
1260 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1266 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", in ath12k_pci_probe()
1267 pci_dev->device); in ath12k_pci_probe()
1268 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1342 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { in ath12k_pci_remove()
1348 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); in ath12k_pci_remove()
1350 cancel_work_sync(&ab->reset_work); in ath12k_pci_remove()