Lines Matching +full:0 +full:x1eb
11 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
13 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
65 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
91 HAL_MACTX_CBF_START = 0 /* 0x0 */,
92 HAL_PHYRX_DATA = 1 /* 0x1 */,
93 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */,
94 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */,
95 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */,
96 HAL_MACTX_DATA_RESP = 5 /* 0x5 */,
97 HAL_MACTX_CBF_DATA = 6 /* 0x6 */,
98 HAL_MACTX_CBF_DONE = 7 /* 0x7 */,
99 HAL_PHYRX_LMR_DATA_RESP = 8 /* 0x8 */,
100 HAL_RXPCU_TO_UCODE_START = 9 /* 0x9 */,
101 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU = 10 /* 0xa */,
102 HAL_RXPCU_TO_UCODE_FULL_MPDU_DATA = 11 /* 0xb */,
103 HAL_RXPCU_TO_UCODE_FCS_STATUS = 12 /* 0xc */,
104 HAL_RXPCU_TO_UCODE_MPDU_DELIMITER = 13 /* 0xd */,
105 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER = 14 /* 0xe */,
106 HAL_RXPCU_TO_UCODE_MPDU_HEADER_DATA = 15 /* 0xf */,
107 HAL_RXPCU_TO_UCODE_END = 16 /* 0x10 */,
108 HAL_MACRX_CBF_READ_REQUEST = 32 /* 0x20 */,
109 HAL_MACRX_CBF_DATA_REQUEST = 33 /* 0x21 */,
110 HAL_MACRXXPECT_NDP_RECEPTION = 34 /* 0x22 */,
111 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 35 /* 0x23 */,
112 HAL_MACRX_NDP_TIMEOUT = 36 /* 0x24 */,
113 HAL_MACRX_ABORT_ACK = 37 /* 0x25 */,
114 HAL_MACRX_REQ_IMPLICIT_FB = 38 /* 0x26 */,
115 HAL_MACRX_CHAIN_MASK = 39 /* 0x27 */,
116 HAL_MACRX_NAP_USER = 40 /* 0x28 */,
117 HAL_MACRX_ABORT_REQUEST = 41 /* 0x29 */,
118 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 42 /* 0x2a */,
119 HAL_PHYTX_ABORT_ACK = 43 /* 0x2b */,
120 HAL_PHYTX_ABORT_REQUEST = 44 /* 0x2c */,
121 HAL_PHYTX_PKT_END = 45 /* 0x2d */,
122 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 46 /* 0x2e */,
123 HAL_PHYTX_REQUEST_CTRL_INFO = 47 /* 0x2f */,
124 HAL_PHYTX_DATA_REQUEST = 48 /* 0x30 */,
125 HAL_PHYTX_BF_CV_LOADING_DONE = 49 /* 0x31 */,
126 HAL_PHYTX_NAP_ACK = 50 /* 0x32 */,
127 HAL_PHYTX_NAP_DONE = 51 /* 0x33 */,
128 HAL_PHYTX_OFF_ACK = 52 /* 0x34 */,
129 HAL_PHYTX_ON_ACK = 53 /* 0x35 */,
130 HAL_PHYTX_SYNTH_OFF_ACK = 54 /* 0x36 */,
131 HAL_PHYTX_DEBUG16 = 55 /* 0x37 */,
132 HAL_MACTX_ABORT_REQUEST = 56 /* 0x38 */,
133 HAL_MACTX_ABORT_ACK = 57 /* 0x39 */,
134 HAL_MACTX_PKT_END = 58 /* 0x3a */,
135 HAL_MACTX_PRE_PHY_DESC = 59 /* 0x3b */,
136 HAL_MACTX_BF_PARAMS_COMMON = 60 /* 0x3c */,
137 HAL_MACTX_BF_PARAMS_PER_USER = 61 /* 0x3d */,
138 HAL_MACTX_PREFETCH_CV = 62 /* 0x3e */,
139 HAL_MACTX_USER_DESC_COMMON = 63 /* 0x3f */,
140 HAL_MACTX_USER_DESC_PER_USER = 64 /* 0x40 */,
141 HAL_XAMPLE_USER_TLV_16 = 65 /* 0x41 */,
142 HAL_XAMPLE_TLV_16 = 66 /* 0x42 */,
143 HAL_MACTX_PHY_OFF = 67 /* 0x43 */,
144 HAL_MACTX_PHY_ON = 68 /* 0x44 */,
145 HAL_MACTX_SYNTH_OFF = 69 /* 0x45 */,
146 HAL_MACTXXPECT_CBF_COMMON = 70 /* 0x46 */,
147 HAL_MACTXXPECT_CBF_PER_USER = 71 /* 0x47 */,
148 HAL_MACTX_PHY_DESC = 72 /* 0x48 */,
149 HAL_MACTX_L_SIG_A = 73 /* 0x49 */,
150 HAL_MACTX_L_SIG_B = 74 /* 0x4a */,
151 HAL_MACTX_HT_SIG = 75 /* 0x4b */,
152 HAL_MACTX_VHT_SIG_A = 76 /* 0x4c */,
153 HAL_MACTX_VHT_SIG_B_SU20 = 77 /* 0x4d */,
154 HAL_MACTX_VHT_SIG_B_SU40 = 78 /* 0x4e */,
155 HAL_MACTX_VHT_SIG_B_SU80 = 79 /* 0x4f */,
156 HAL_MACTX_VHT_SIG_B_SU160 = 80 /* 0x50 */,
157 HAL_MACTX_VHT_SIG_B_MU20 = 81 /* 0x51 */,
158 HAL_MACTX_VHT_SIG_B_MU40 = 82 /* 0x52 */,
159 HAL_MACTX_VHT_SIG_B_MU80 = 83 /* 0x53 */,
160 HAL_MACTX_VHT_SIG_B_MU160 = 84 /* 0x54 */,
161 HAL_MACTX_SERVICE = 85 /* 0x55 */,
162 HAL_MACTX_HE_SIG_A_SU = 86 /* 0x56 */,
163 HAL_MACTX_HE_SIG_A_MU_DL = 87 /* 0x57 */,
164 HAL_MACTX_HE_SIG_A_MU_UL = 88 /* 0x58 */,
165 HAL_MACTX_HE_SIG_B1_MU = 89 /* 0x59 */,
166 HAL_MACTX_HE_SIG_B2_MU = 90 /* 0x5a */,
167 HAL_MACTX_HE_SIG_B2_OFDMA = 91 /* 0x5b */,
168 HAL_MACTX_DELETE_CV = 92 /* 0x5c */,
169 HAL_MACTX_MU_UPLINK_COMMON = 93 /* 0x5d */,
170 HAL_MACTX_MU_UPLINK_USER_SETUP = 94 /* 0x5e */,
171 HAL_MACTX_OTHER_TRANSMIT_INFO = 95 /* 0x5f */,
172 HAL_MACTX_PHY_NAP = 96 /* 0x60 */,
173 HAL_MACTX_DEBUG = 97 /* 0x61 */,
174 HAL_PHYRX_ABORT_ACK = 98 /* 0x62 */,
175 HAL_PHYRX_GENERATED_CBF_DETAILS = 99 /* 0x63 */,
176 HAL_PHYRX_RSSI_LEGACY = 100 /* 0x64 */,
177 HAL_PHYRX_RSSI_HT = 101 /* 0x65 */,
178 HAL_PHYRX_USER_INFO = 102 /* 0x66 */,
179 HAL_PHYRX_PKT_END = 103 /* 0x67 */,
180 HAL_PHYRX_DEBUG = 104 /* 0x68 */,
181 HAL_PHYRX_CBF_TRANSFER_DONE = 105 /* 0x69 */,
182 HAL_PHYRX_CBF_TRANSFER_ABORT = 106 /* 0x6a */,
183 HAL_PHYRX_L_SIG_A = 107 /* 0x6b */,
184 HAL_PHYRX_L_SIG_B = 108 /* 0x6c */,
185 HAL_PHYRX_HT_SIG = 109 /* 0x6d */,
186 HAL_PHYRX_VHT_SIG_A = 110 /* 0x6e */,
187 HAL_PHYRX_VHT_SIG_B_SU20 = 111 /* 0x6f */,
188 HAL_PHYRX_VHT_SIG_B_SU40 = 112 /* 0x70 */,
189 HAL_PHYRX_VHT_SIG_B_SU80 = 113 /* 0x71 */,
190 HAL_PHYRX_VHT_SIG_B_SU160 = 114 /* 0x72 */,
191 HAL_PHYRX_VHT_SIG_B_MU20 = 115 /* 0x73 */,
192 HAL_PHYRX_VHT_SIG_B_MU40 = 116 /* 0x74 */,
193 HAL_PHYRX_VHT_SIG_B_MU80 = 117 /* 0x75 */,
194 HAL_PHYRX_VHT_SIG_B_MU160 = 118 /* 0x76 */,
195 HAL_PHYRX_HE_SIG_A_SU = 119 /* 0x77 */,
196 HAL_PHYRX_HE_SIG_A_MU_DL = 120 /* 0x78 */,
197 HAL_PHYRX_HE_SIG_A_MU_UL = 121 /* 0x79 */,
198 HAL_PHYRX_HE_SIG_B1_MU = 122 /* 0x7a */,
199 HAL_PHYRX_HE_SIG_B2_MU = 123 /* 0x7b */,
200 HAL_PHYRX_HE_SIG_B2_OFDMA = 124 /* 0x7c */,
201 HAL_PHYRX_OTHER_RECEIVE_INFO = 125 /* 0x7d */,
202 HAL_PHYRX_COMMON_USER_INFO = 126 /* 0x7e */,
203 HAL_PHYRX_DATA_DONE = 127 /* 0x7f */,
204 HAL_COEX_TX_REQ = 128 /* 0x80 */,
205 HAL_DUMMY = 129 /* 0x81 */,
206 HALXAMPLE_TLV_32_NAME = 130 /* 0x82 */,
207 HAL_MPDU_LIMIT = 131 /* 0x83 */,
208 HAL_NA_LENGTH_END = 132 /* 0x84 */,
209 HAL_OLE_BUF_STATUS = 133 /* 0x85 */,
210 HAL_PCU_PPDU_SETUP_DONE = 134 /* 0x86 */,
211 HAL_PCU_PPDU_SETUP_END = 135 /* 0x87 */,
212 HAL_PCU_PPDU_SETUP_INIT = 136 /* 0x88 */,
213 HAL_PCU_PPDU_SETUP_START = 137 /* 0x89 */,
214 HAL_PDG_FES_SETUP = 138 /* 0x8a */,
215 HAL_PDG_RESPONSE = 139 /* 0x8b */,
216 HAL_PDG_TX_REQ = 140 /* 0x8c */,
217 HAL_SCH_WAIT_INSTR = 141 /* 0x8d */,
218 HAL_TQM_FLOWMPTY_STATUS = 143 /* 0x8f */,
219 HAL_TQM_FLOW_NOTMPTY_STATUS = 144 /* 0x90 */,
220 HAL_TQM_GEN_MPDU_LENGTH_LIST = 145 /* 0x91 */,
221 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 146 /* 0x92 */,
222 HAL_TQM_GEN_MPDUS = 147 /* 0x93 */,
223 HAL_TQM_GEN_MPDUS_STATUS = 148 /* 0x94 */,
224 HAL_TQM_REMOVE_MPDU = 149 /* 0x95 */,
225 HAL_TQM_REMOVE_MPDU_STATUS = 150 /* 0x96 */,
226 HAL_TQM_REMOVE_MSDU = 151 /* 0x97 */,
227 HAL_TQM_REMOVE_MSDU_STATUS = 152 /* 0x98 */,
228 HAL_TQM_UPDATE_TX_MPDU_COUNT = 153 /* 0x99 */,
229 HAL_TQM_WRITE_CMD = 154 /* 0x9a */,
230 HAL_OFDMA_TRIGGER_DETAILS = 155 /* 0x9b */,
231 HAL_TX_DATA = 156 /* 0x9c */,
232 HAL_TX_FES_SETUP = 157 /* 0x9d */,
233 HAL_RX_PACKET = 158 /* 0x9e */,
234 HALXPECTED_RESPONSE = 159 /* 0x9f */,
235 HAL_TX_MPDU_END = 160 /* 0xa0 */,
236 HAL_TX_MPDU_START = 161 /* 0xa1 */,
237 HAL_TX_MSDU_END = 162 /* 0xa2 */,
238 HAL_TX_MSDU_START = 163 /* 0xa3 */,
239 HAL_TX_SW_MODE_SETUP = 164 /* 0xa4 */,
240 HAL_TXPCU_BUFFER_STATUS = 165 /* 0xa5 */,
241 HAL_TXPCU_USER_BUFFER_STATUS = 166 /* 0xa6 */,
242 HAL_DATA_TO_TIME_CONFIG = 167 /* 0xa7 */,
243 HALXAMPLE_USER_TLV_32 = 168 /* 0xa8 */,
244 HAL_MPDU_INFO = 169 /* 0xa9 */,
245 HAL_PDG_USER_SETUP = 170 /* 0xaa */,
246 HAL_TX_11AH_SETUP = 171 /* 0xab */,
247 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 172 /* 0xac */,
248 HAL_TX_PEER_ENTRY = 173 /* 0xad */,
249 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 174 /* 0xae */,
250 HALXAMPLE_USER_TLV_44 = 175 /* 0xaf */,
251 HAL_TX_FLUSH = 176 /* 0xb0 */,
252 HAL_TX_FLUSH_REQ = 177 /* 0xb1 */,
253 HAL_TQM_WRITE_CMD_STATUS = 178 /* 0xb2 */,
254 HAL_TQM_GET_MPDU_QUEUE_STATS = 179 /* 0xb3 */,
255 HAL_TQM_GET_MSDU_FLOW_STATS = 180 /* 0xb4 */,
256 HALXAMPLE_USER_CTLV_44 = 181 /* 0xb5 */,
257 HAL_TX_FES_STATUS_START = 182 /* 0xb6 */,
258 HAL_TX_FES_STATUS_USER_PPDU = 183 /* 0xb7 */,
259 HAL_TX_FES_STATUS_USER_RESPONSE = 184 /* 0xb8 */,
260 HAL_TX_FES_STATUS_END = 185 /* 0xb9 */,
261 HAL_RX_TRIG_INFO = 186 /* 0xba */,
262 HAL_RXPCU_TX_SETUP_CLEAR = 187 /* 0xbb */,
263 HAL_RX_FRAME_BITMAP_REQ = 188 /* 0xbc */,
264 HAL_RX_FRAME_BITMAP_ACK = 189 /* 0xbd */,
265 HAL_COEX_RX_STATUS = 190 /* 0xbe */,
266 HAL_RX_START_PARAM = 191 /* 0xbf */,
267 HAL_RX_PPDU_START = 192 /* 0xc0 */,
268 HAL_RX_PPDU_END = 193 /* 0xc1 */,
269 HAL_RX_MPDU_START = 194 /* 0xc2 */,
270 HAL_RX_MPDU_END = 195 /* 0xc3 */,
271 HAL_RX_MSDU_START = 196 /* 0xc4 */,
272 HAL_RX_MSDU_END = 197 /* 0xc5 */,
273 HAL_RX_ATTENTION = 198 /* 0xc6 */,
274 HAL_RECEIVED_RESPONSE_INFO = 199 /* 0xc7 */,
275 HAL_RX_PHY_SLEEP = 200 /* 0xc8 */,
276 HAL_RX_HEADER = 201 /* 0xc9 */,
277 HAL_RX_PEER_ENTRY = 202 /* 0xca */,
278 HAL_RX_FLUSH = 203 /* 0xcb */,
279 HAL_RX_RESPONSE_REQUIRED_INFO = 204 /* 0xcc */,
280 HAL_RX_FRAMELESS_BAR_DETAILS = 205 /* 0xcd */,
281 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 206 /* 0xce */,
282 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 207 /* 0xcf */,
283 HAL_TX_CBF_INFO = 208 /* 0xd0 */,
284 HAL_PCU_PPDU_SETUP_USER = 209 /* 0xd1 */,
285 HAL_RX_MPDU_PCU_START = 210 /* 0xd2 */,
286 HAL_RX_PM_INFO = 211 /* 0xd3 */,
287 HAL_RX_USER_PPDU_END = 212 /* 0xd4 */,
288 HAL_RX_PRE_PPDU_START = 213 /* 0xd5 */,
289 HAL_RX_PREAMBLE = 214 /* 0xd6 */,
290 HAL_TX_FES_SETUP_COMPLETE = 215 /* 0xd7 */,
291 HAL_TX_LAST_MPDU_FETCHED = 216 /* 0xd8 */,
292 HAL_TXDMA_STOP_REQUEST = 217 /* 0xd9 */,
293 HAL_RXPCU_SETUP = 218 /* 0xda */,
294 HAL_RXPCU_USER_SETUP = 219 /* 0xdb */,
295 HAL_TX_FES_STATUS_ACK_OR_BA = 220 /* 0xdc */,
296 HAL_TQM_ACKED_MPDU = 221 /* 0xdd */,
297 HAL_COEX_TX_RESP = 222 /* 0xde */,
298 HAL_COEX_TX_STATUS = 223 /* 0xdf */,
299 HAL_MACTX_COEX_PHY_CTRL = 224 /* 0xe0 */,
300 HAL_COEX_STATUS_BROADCAST = 225 /* 0xe1 */,
301 HAL_RESPONSE_START_STATUS = 226 /* 0xe2 */,
302 HAL_RESPONSEND_STATUS = 227 /* 0xe3 */,
303 HAL_CRYPTO_STATUS = 228 /* 0xe4 */,
304 HAL_RECEIVED_TRIGGER_INFO = 229 /* 0xe5 */,
305 HAL_COEX_TX_STOP_CTRL = 230 /* 0xe6 */,
306 HAL_RX_PPDU_ACK_REPORT = 231 /* 0xe7 */,
307 HAL_RX_PPDU_NO_ACK_REPORT = 232 /* 0xe8 */,
308 HAL_SCH_COEX_STATUS = 233 /* 0xe9 */,
309 HAL_SCHEDULER_COMMAND_STATUS = 234 /* 0xea */,
310 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 235 /* 0xeb */,
311 HAL_TX_FES_STATUS_PROT = 236 /* 0xec */,
312 HAL_TX_FES_STATUS_START_PPDU = 237 /* 0xed */,
313 HAL_TX_FES_STATUS_START_PROT = 238 /* 0xee */,
314 HAL_TXPCU_PHYTX_DEBUG32 = 239 /* 0xef */,
315 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 240 /* 0xf0 */,
316 HAL_TX_MPDU_COUNT_TRANSFERND = 241 /* 0xf1 */,
317 HAL_WHO_ANCHOR_OFFSET = 242 /* 0xf2 */,
318 HAL_WHO_ANCHOR_VALUE = 243 /* 0xf3 */,
319 HAL_WHO_CCE_INFO = 244 /* 0xf4 */,
320 HAL_WHO_COMMIT = 245 /* 0xf5 */,
321 HAL_WHO_COMMIT_DONE = 246 /* 0xf6 */,
322 HAL_WHO_FLUSH = 247 /* 0xf7 */,
323 HAL_WHO_L2_LLC = 248 /* 0xf8 */,
324 HAL_WHO_L2_PAYLOAD = 249 /* 0xf9 */,
325 HAL_WHO_L3_CHECKSUM = 250 /* 0xfa */,
326 HAL_WHO_L3_INFO = 251 /* 0xfb */,
327 HAL_WHO_L4_CHECKSUM = 252 /* 0xfc */,
328 HAL_WHO_L4_INFO = 253 /* 0xfd */,
329 HAL_WHO_MSDU = 254 /* 0xfe */,
330 HAL_WHO_MSDU_MISC = 255 /* 0xff */,
331 HAL_WHO_PACKET_DATA = 256 /* 0x100 */,
332 HAL_WHO_PACKET_HDR = 257 /* 0x101 */,
333 HAL_WHO_PPDU_END = 258 /* 0x102 */,
334 HAL_WHO_PPDU_START = 259 /* 0x103 */,
335 HAL_WHO_TSO = 260 /* 0x104 */,
336 HAL_WHO_WMAC_HEADER_PV0 = 261 /* 0x105 */,
337 HAL_WHO_WMAC_HEADER_PV1 = 262 /* 0x106 */,
338 HAL_WHO_WMAC_IV = 263 /* 0x107 */,
339 HAL_MPDU_INFO_END = 264 /* 0x108 */,
340 HAL_MPDU_INFO_BITMAP = 265 /* 0x109 */,
341 HAL_TX_QUEUE_EXTENSION = 266 /* 0x10a */,
342 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 267 /* 0x10b */,
343 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 268 /* 0x10c */,
344 HAL_TQM_ACKED_MPDU_STATUS = 269 /* 0x10d */,
345 HAL_TQM_ADD_MSDU_STATUS = 270 /* 0x10e */,
346 HAL_TQM_LIST_GEN_DONE = 271 /* 0x10f */,
347 HAL_WHO_TERMINATE = 272 /* 0x110 */,
348 HAL_TX_LAST_MPDU_END = 273 /* 0x111 */,
349 HAL_TX_CV_DATA = 274 /* 0x112 */,
350 HAL_PPDU_TX_END = 275 /* 0x113 */,
351 HAL_PROT_TX_END = 276 /* 0x114 */,
352 HAL_MPDU_INFO_GLOBAL_END = 277 /* 0x115 */,
353 HAL_TQM_SCH_INSTR_GLOBAL_END = 278 /* 0x116 */,
354 HAL_RX_PPDU_END_USER_STATS = 279 /* 0x117 */,
355 HAL_RX_PPDU_END_USER_STATS_EXT = 280 /* 0x118 */,
356 HAL_REO_GET_QUEUE_STATS = 281 /* 0x119 */,
357 HAL_REO_FLUSH_QUEUE = 282 /* 0x11a */,
358 HAL_REO_FLUSH_CACHE = 283 /* 0x11b */,
359 HAL_REO_UNBLOCK_CACHE = 284 /* 0x11c */,
360 HAL_REO_GET_QUEUE_STATS_STATUS = 285 /* 0x11d */,
361 HAL_REO_FLUSH_QUEUE_STATUS = 286 /* 0x11e */,
362 HAL_REO_FLUSH_CACHE_STATUS = 287 /* 0x11f */,
363 HAL_REO_UNBLOCK_CACHE_STATUS = 288 /* 0x120 */,
364 HAL_TQM_FLUSH_CACHE = 289 /* 0x121 */,
365 HAL_TQM_UNBLOCK_CACHE = 290 /* 0x122 */,
366 HAL_TQM_FLUSH_CACHE_STATUS = 291 /* 0x123 */,
367 HAL_TQM_UNBLOCK_CACHE_STATUS = 292 /* 0x124 */,
368 HAL_RX_PPDU_END_STATUS_DONE = 293 /* 0x125 */,
369 HAL_RX_STATUS_BUFFER_DONE = 294 /* 0x126 */,
370 HAL_TX_DATA_SYNC = 297 /* 0x129 */,
371 HAL_PHYRX_CBF_READ_REQUEST_ACK = 298 /* 0x12a */,
372 HAL_TQM_GET_MPDU_HEAD_INFO = 299 /* 0x12b */,
373 HAL_TQM_SYNC_CMD = 300 /* 0x12c */,
374 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 301 /* 0x12d */,
375 HAL_TQM_SYNC_CMD_STATUS = 302 /* 0x12e */,
376 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 303 /* 0x12f */,
377 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 304 /* 0x130 */,
378 HAL_REO_FLUSH_TIMEOUT_LIST = 305 /* 0x131 */,
379 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 306 /* 0x132 */,
380 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 307 /* 0x133 */,
381 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 308 /* 0x134 */,
382 HALXAMPLE_USER_TLV_32_NAME = 309 /* 0x135 */,
383 HAL_RX_PPDU_START_USER_INFO = 310 /* 0x136 */,
384 HAL_RX_RING_MASK = 311 /* 0x137 */,
385 HAL_COEX_MAC_NAP = 312 /* 0x138 */,
386 HAL_RXPCU_PPDU_END_INFO = 313 /* 0x139 */,
387 HAL_WHO_MESH_CONTROL = 314 /* 0x13a */,
388 HAL_PDG_SW_MODE_BW_START = 315 /* 0x13b */,
389 HAL_PDG_SW_MODE_BW_END = 316 /* 0x13c */,
390 HAL_PDG_WAIT_FOR_MAC_REQUEST = 317 /* 0x13d */,
391 HAL_PDG_WAIT_FOR_PHY_REQUEST = 318 /* 0x13e */,
392 HAL_SCHEDULER_END = 319 /* 0x13f */,
393 HAL_RX_PPDU_START_DROPPED = 320 /* 0x140 */,
394 HAL_RX_PPDU_END_DROPPED = 321 /* 0x141 */,
395 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 322 /* 0x142 */,
396 HAL_RX_MPDU_START_DROPPED = 323 /* 0x143 */,
397 HAL_RX_MSDU_START_DROPPED = 324 /* 0x144 */,
398 HAL_RX_MSDU_END_DROPPED = 325 /* 0x145 */,
399 HAL_RX_MPDU_END_DROPPED = 326 /* 0x146 */,
400 HAL_RX_ATTENTION_DROPPED = 327 /* 0x147 */,
401 HAL_TXPCU_USER_SETUP = 328 /* 0x148 */,
402 HAL_RXPCU_USER_SETUP_EXT = 329 /* 0x149 */,
403 HAL_CMD_PART_0_END = 330 /* 0x14a */,
404 HAL_MACTX_SYNTH_ON = 331 /* 0x14b */,
405 HAL_SCH_CRITICAL_TLV_REFERENCE = 332 /* 0x14c */,
406 HAL_TQM_MPDU_GLOBAL_START = 333 /* 0x14d */,
407 HALXAMPLE_TLV_32 = 334 /* 0x14e */,
408 HAL_TQM_UPDATE_TX_MSDU_FLOW = 335 /* 0x14f */,
409 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 336 /* 0x150 */,
410 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 337 /* 0x151 */,
411 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 338 /* 0x152 */,
412 HAL_REO_UPDATE_RX_REO_QUEUE = 339 /* 0x153 */,
413 HAL_TQM_MPDU_QUEUEMPTY_STATUS = 340 /* 0x154 */,
414 HAL_TQM_2_SCH_MPDU_AVAILABLE = 341 /* 0x155 */,
415 HAL_PDG_TRIG_RESPONSE = 342 /* 0x156 */,
416 HAL_TRIGGER_RESPONSE_TX_DONE = 343 /* 0x157 */,
417 HAL_ABORT_FROM_PHYRX_DETAILS = 344 /* 0x158 */,
418 HAL_SCH_TQM_CMD_WRAPPER = 345 /* 0x159 */,
419 HAL_MPDUS_AVAILABLE = 346 /* 0x15a */,
420 HAL_RECEIVED_RESPONSE_INFO_PART2 = 347 /* 0x15b */,
421 HAL_PHYRX_TX_START_TIMING = 348 /* 0x15c */,
422 HAL_TXPCU_PREAMBLE_DONE = 349 /* 0x15d */,
423 HAL_NDP_PREAMBLE_DONE = 350 /* 0x15e */,
424 HAL_SCH_TQM_CMD_WRAPPER_RBO_DROP = 351 /* 0x15f */,
425 HAL_SCH_TQM_CMD_WRAPPER_CONT_DROP = 352 /* 0x160 */,
426 HAL_MACTX_CLEAR_PREV_TX_INFO = 353 /* 0x161 */,
427 HAL_TX_PUNCTURE_SETUP = 354 /* 0x162 */,
428 HAL_R2R_STATUS_END = 355 /* 0x163 */,
429 HAL_MACTX_PREFETCH_CV_COMMON = 356 /* 0x164 */,
430 HAL_END_OF_FLUSH_MARKER = 357 /* 0x165 */,
431 HAL_MACTX_MU_UPLINK_COMMON_PUNC = 358 /* 0x166 */,
432 HAL_MACTX_MU_UPLINK_USER_SETUP_PUNC = 359 /* 0x167 */,
433 HAL_RECEIVED_RESPONSE_USER_7_0 = 360 /* 0x168 */,
434 HAL_RECEIVED_RESPONSE_USER_15_8 = 361 /* 0x169 */,
435 HAL_RECEIVED_RESPONSE_USER_23_16 = 362 /* 0x16a */,
436 HAL_RECEIVED_RESPONSE_USER_31_24 = 363 /* 0x16b */,
437 HAL_RECEIVED_RESPONSE_USER_36_32 = 364 /* 0x16c */,
438 HAL_TX_LOOPBACK_SETUP = 365 /* 0x16d */,
439 HAL_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS = 366 /* 0x16e */,
440 HAL_SCH_WAIT_INSTR_TX_PATH = 367 /* 0x16f */,
441 HAL_MACTX_OTHER_TRANSMIT_INFO_TX2TX = 368 /* 0x170 */,
442 HAL_MACTX_OTHER_TRANSMIT_INFOMUPHY_SETUP = 369 /* 0x171 */,
443 HAL_PHYRX_OTHER_RECEIVE_INFOVM_DETAILS = 370 /* 0x172 */,
444 HAL_TX_WUR_DATA = 371 /* 0x173 */,
445 HAL_RX_PPDU_END_START = 372 /* 0x174 */,
446 HAL_RX_PPDU_END_MIDDLE = 373 /* 0x175 */,
447 HAL_RX_PPDU_END_LAST = 374 /* 0x176 */,
448 HAL_MACTX_BACKOFF_BASED_TRANSMISSION = 375 /* 0x177 */,
449 HAL_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX = 376 /* 0x178 */,
450 HAL_SRP_INFO = 377 /* 0x179 */,
451 HAL_OBSS_SR_INFO = 378 /* 0x17a */,
452 HAL_SCHEDULER_SW_MSG_STATUS = 379 /* 0x17b */,
453 HAL_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT = 380 /* 0x17c */,
454 HAL_RXPCU_SETUP_COMPLETE = 381 /* 0x17d */,
455 HAL_SNOOP_PPDU_START = 382 /* 0x17e */,
456 HAL_SNOOP_MPDU_USR_DBG_INFO = 383 /* 0x17f */,
457 HAL_SNOOP_MSDU_USR_DBG_INFO = 384 /* 0x180 */,
458 HAL_SNOOP_MSDU_USR_DATA = 385 /* 0x181 */,
459 HAL_SNOOP_MPDU_USR_STAT_INFO = 386 /* 0x182 */,
460 HAL_SNOOP_PPDU_END = 387 /* 0x183 */,
461 HAL_SNOOP_SPARE = 388 /* 0x184 */,
462 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON = 390 /* 0x186 */,
463 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER = 391 /* 0x187 */,
464 HAL_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS = 392 /* 0x188 */,
465 HAL_PHYRX_OTHER_RECEIVE_INFO_108PVM_DETAILS = 393 /* 0x189 */,
466 HAL_SCH_TLV_WRAPPER = 394 /* 0x18a */,
467 HAL_SCHEDULER_STATUS_WRAPPER = 395 /* 0x18b */,
468 HAL_MPDU_INFO_6X = 396 /* 0x18c */,
469 HAL_MACTX_11AZ_USER_DESC_PER_USER = 397 /* 0x18d */,
470 HAL_MACTX_U_SIGHT_SU_MU = 398 /* 0x18e */,
471 HAL_MACTX_U_SIGHT_TB = 399 /* 0x18f */,
472 HAL_PHYRX_U_SIGHT_SU_MU = 403 /* 0x193 */,
473 HAL_PHYRX_U_SIGHT_TB = 404 /* 0x194 */,
474 HAL_MACRX_LMR_READ_REQUEST = 408 /* 0x198 */,
475 HAL_MACRX_LMR_DATA_REQUEST = 409 /* 0x199 */,
476 HAL_PHYRX_LMR_TRANSFER_DONE = 410 /* 0x19a */,
477 HAL_PHYRX_LMR_TRANSFER_ABORT = 411 /* 0x19b */,
478 HAL_PHYRX_LMR_READ_REQUEST_ACK = 412 /* 0x19c */,
479 HAL_MACRX_SECURE_LTF_SEQ_PTR = 413 /* 0x19d */,
480 HAL_PHYRX_USER_INFO_MU_UL = 414 /* 0x19e */,
481 HAL_MPDU_QUEUE_OVERVIEW = 415 /* 0x19f */,
482 HAL_SCHEDULER_NAV_INFO = 416 /* 0x1a0 */,
483 HAL_LMR_PEER_ENTRY = 418 /* 0x1a2 */,
484 HAL_LMR_MPDU_START = 419 /* 0x1a3 */,
485 HAL_LMR_DATA = 420 /* 0x1a4 */,
486 HAL_LMR_MPDU_END = 421 /* 0x1a5 */,
487 HAL_REO_GET_QUEUE_1K_STATS_STATUS = 422 /* 0x1a6 */,
488 HAL_RX_FRAME_1K_BITMAP_ACK = 423 /* 0x1a7 */,
489 HAL_TX_FES_STATUS_1K_BA = 424 /* 0x1a8 */,
490 HAL_TQM_ACKED_1K_MPDU = 425 /* 0x1a9 */,
491 HAL_MACRX_INBSS_OBSS_IND = 426 /* 0x1aa */,
492 HAL_PHYRX_LOCATION = 427 /* 0x1ab */,
493 HAL_MLO_TX_NOTIFICATION_SU = 428 /* 0x1ac */,
494 HAL_MLO_TX_NOTIFICATION_MU = 429 /* 0x1ad */,
495 HAL_MLO_TX_REQ_SU = 430 /* 0x1ae */,
496 HAL_MLO_TX_REQ_MU = 431 /* 0x1af */,
497 HAL_MLO_TX_RESP = 432 /* 0x1b0 */,
498 HAL_MLO_RX_NOTIFICATION = 433 /* 0x1b1 */,
499 HAL_MLO_BKOFF_TRUNC_REQ = 434 /* 0x1b2 */,
500 HAL_MLO_TBTT_NOTIFICATION = 435 /* 0x1b3 */,
501 HAL_MLO_MESSAGE = 436 /* 0x1b4 */,
502 HAL_MLO_TS_SYNC_MSG = 437 /* 0x1b5 */,
503 HAL_MLO_FES_SETUP = 438 /* 0x1b6 */,
504 HAL_MLO_PDG_FES_SETUP_SU = 439 /* 0x1b7 */,
505 HAL_MLO_PDG_FES_SETUP_MU = 440 /* 0x1b8 */,
506 HAL_MPDU_INFO_1K_BITMAP = 441 /* 0x1b9 */,
507 HAL_MON_BUF_ADDR = 442 /* 0x1ba */,
508 HAL_TX_FRAG_STATE = 443 /* 0x1bb */,
509 HAL_MACTXHT_SIG_USR_OFDMA = 446 /* 0x1be */,
510 HAL_PHYRXHT_SIG_CMN_PUNC = 448 /* 0x1c0 */,
511 HAL_PHYRXHT_SIG_CMN_OFDMA = 450 /* 0x1c2 */,
512 HAL_PHYRXHT_SIG_USR_OFDMA = 454 /* 0x1c6 */,
513 HAL_PHYRX_PKT_END_PART1 = 456 /* 0x1c8 */,
514 HAL_MACTXXPECT_NDP_RECEPTION = 457 /* 0x1c9 */,
515 HAL_MACTX_SECURE_LTF_SEQ_PTR = 458 /* 0x1ca */,
516 HAL_MLO_PDG_BKOFF_TRUNC_NOTIFY = 460 /* 0x1cc */,
517 HAL_PHYRX_11AZ_INTEGRITY_DATA = 461 /* 0x1cd */,
518 HAL_PHYTX_LOCATION = 462 /* 0x1ce */,
519 HAL_PHYTX_11AZ_INTEGRITY_DATA = 463 /* 0x1cf */,
520 HAL_MACTXHT_SIG_USR_SU = 466 /* 0x1d2 */,
521 HAL_MACTXHT_SIG_USR_MU_MIMO = 467 /* 0x1d3 */,
522 HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */,
523 HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */,
524 HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */,
525 HAL_PHYRX_GENERICHT_SIG = 471 /* 0x1d7 */,
526 HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */,
527 HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */,
528 HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */,
529 HAL_OVERWRITE_RESP_END = 475 /* 0x1db */,
530 HAL_RXPCUARLY_RX_INDICATION = 476 /* 0x1dc */,
531 HAL_MON_DROP = 477 /* 0x1dd */,
532 HAL_MACRX_MU_UPLINK_COMMON_SNIFF = 478 /* 0x1de */,
533 HAL_MACRX_MU_UPLINK_USER_SETUP_SNIFF = 479 /* 0x1df */,
534 HAL_MACRX_MU_UPLINK_USER_SEL_SNIFF = 480 /* 0x1e0 */,
535 HAL_MACRX_MU_UPLINK_FCS_STATUS_SNIFF = 481 /* 0x1e1 */,
536 HAL_MACTX_PREFETCH_CV_DMA = 482 /* 0x1e2 */,
537 HAL_MACTX_PREFETCH_CV_PER_USER = 483 /* 0x1e3 */,
538 HAL_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS = 484 /* 0x1e4 */,
539 HAL_MACTX_BF_PARAMS_UPDATE_COMMON = 485 /* 0x1e5 */,
540 HAL_MACTX_BF_PARAMS_UPDATE_PER_USER = 486 /* 0x1e6 */,
541 HAL_RANGING_USER_DETAILS = 487 /* 0x1e7 */,
542 HAL_PHYTX_CV_CORR_STATUS = 488 /* 0x1e8 */,
543 HAL_PHYTX_CV_CORR_COMMON = 489 /* 0x1e9 */,
544 HAL_PHYTX_CV_CORR_USER = 490 /* 0x1ea */,
545 HAL_MACTX_CV_CORR_COMMON = 491 /* 0x1eb */,
546 HAL_MACTX_CV_CORR_MAC_INFO_GROUP = 492 /* 0x1ec */,
547 HAL_BW_PUNCTUREVAL_WRAPPER = 493 /* 0x1ed */,
548 HAL_MACTX_RX_NOTIFICATION_FOR_PHY = 494 /* 0x1ee */,
549 HAL_MACTX_TX_NOTIFICATION_FOR_PHY = 495 /* 0x1ef */,
550 HAL_MACTX_MU_UPLINK_COMMON_PER_BW = 496 /* 0x1f0 */,
551 HAL_MACTX_MU_UPLINK_USER_SETUP_PER_BW = 497 /* 0x1f1 */,
552 HAL_RX_PPDU_END_USER_STATS_EXT2 = 498 /* 0x1f2 */,
553 HAL_FW2SW_MON = 499 /* 0x1f3 */,
554 HAL_WSI_DIRECT_MESSAGE = 500 /* 0x1f4 */,
555 HAL_MACTXMLSR_PRE_SWITCH = 501 /* 0x1f5 */,
556 HAL_MACTXMLSR_SWITCH = 502 /* 0x1f6 */,
557 HAL_MACTXMLSR_SWITCH_BACK = 503 /* 0x1f7 */,
558 HAL_PHYTXMLSR_SWITCH_ACK = 504 /* 0x1f8 */,
559 HAL_PHYTXMLSR_SWITCH_BACK_ACK = 505 /* 0x1f9 */,
560 HAL_SPARE_REUSE_TAG_0 = 506 /* 0x1fa */,
561 HAL_SPARE_REUSE_TAG_1 = 507 /* 0x1fb */,
562 HAL_SPARE_REUSE_TAG_2 = 508 /* 0x1fc */,
563 HAL_SPARE_REUSE_TAG_3 = 509 /* 0x1fd */,
566 HAL_TLV_BASE = 511 /* 0x1ff */,
588 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0)
601 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0)
668 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0)
699 * 'Msdu_continuation' set to 0. This implies that when an msdu
769 #define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0)
828 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(0)
906 * Set to value 0x8 when msdu capture mode is enabled for this ring
910 * 0 - Idle ring
918 #define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0)
954 * Disabled: 0 (Default)
958 * Disabled: 0 (Default)
1004 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1009 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0)
1018 #define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0)
1125 * 0 - Idle ring
1133 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0)
1140 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
1182 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0)
1193 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0)
1208 #define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE BIT(0)
1218 #define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0)
1227 #define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE BIT(0)
1236 #define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0)
1351 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4
1360 * 0: To choose Flow 0 and 1 of any TID use this value.
1367 * to 0 use flows 0 and 1.
1378 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0)
1415 * 0 refers to the IDLE ring
1424 * At initialization time, this value is set to 0. On the
1427 * count value continues with 0 again.
1442 #define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0)
1444 #define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0)
1499 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1506 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0)
1533 * each dword read (4 bytes), the byte 0 is swapped with byte 3
1540 * For each dword write (4 bytes), the byte 0 is swapped with
1570 * 0 refers to the IDLE ring
1579 * At initialization time, this value is set to 0. On the
1582 * count value continues with 0 again.
1595 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0)
1619 * 0 refers to the IDLE ring
1628 * At initialization time, this value is set to 0. On the
1631 * count value continues with 0 again.
1650 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0)
1701 * 0 refers to the IDLE ring
1710 * At initialization time, this value is set to 0. On the
1713 * count value continues with 0 again.
1726 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0)
1832 * set to value 0, which represents the 'NULL' pointer. When all MSDU
1836 #define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1846 #define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0)
1860 #define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1869 #define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1873 #define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1879 #define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0)
1894 #define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1903 #define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0)
1907 #define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0)
1913 #define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0)
1927 #define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1963 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0)
1972 #define HAL_WBM_RELEASE_INFO3_FIRST_MSDU BIT(0)
2019 * At initialization time, this value is set to 0. On the
2022 * count value continues with 0 again.
2074 #define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0)
2081 #define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0)
2103 * only if end_of_ppdu is set to 0.
2108 * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU
2114 * <enum 0 rxdma_error_detected> RXDMA detected an error an
2131 * <enum 0 rxdma_overflow_err>MPDU frame is not complete
2177 * end_of_ppdu is set to 0.
2200 * All other fields shall be set to 0.
2205 * if end_of_ppdu = 0, or the PPDU whose end is indicated
2216 * Frameless_bar are all set to 0.
2218 * Otherwise this bit is set to 0.
2240 * At initialization time, this value is set to 0. On the
2243 * count value continues with 0 again.
2282 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
2300 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0)
2334 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0)
2336 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0)
2353 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0)
2360 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0)
2367 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0)
2370 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0)
2432 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
2433 * session, with window size of 0). The 3 values here are the main values
2436 * A BA window size of 0 (=> one frame entry bitmat), means that there is
2462 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0)
2487 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0)
2503 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0)
2520 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0)
2536 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0)
2563 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0)
2566 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0)
2569 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0)
2574 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0)
2577 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0)
2673 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0)
2675 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0)
2695 * 0 - No error has been detected while executing this command
2704 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2730 * 0 - No error has been detected while executing this command
2736 * 0 - No blocking related errors found
2744 * 0 - miss; 1 - hit
2752 * In REO, this is always 0
2757 * 0 - No error found
2771 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0)
2790 * 0 - No error has been detected while executing this command
2796 * 0 - Unblock a blocking resource
2804 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0)
2807 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0)
2827 * 0 - No error has been detected while executing this command
2847 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0)
2848 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0)
2849 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0)
2850 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0)
2851 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0)
2886 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0)
2913 * bit range 7-0 : upper 8 bit of the physical address.
2919 #define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0)
2921 #define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(15, 0)
2940 * bit 0 -17 buf_id to track the skb's vaddr.