1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
13 	"mhi-er0",
14 	"mhi-er1",
27 	"host2wbm-desc-feed",
28 	"host2reo-re-injection",
29 	"host2reo-command",
30 	"host2rxdma-monitor-ring3",
31 	"host2rxdma-monitor-ring2",
32 	"host2rxdma-monitor-ring1",
33 	"reo2ost-exception",
34 	"wbm2host-rx-release",
35 	"reo2host-status",
36 	"reo2host-destination-ring4",
37 	"reo2host-destination-ring3",
38 	"reo2host-destination-ring2",
39 	"reo2host-destination-ring1",
40 	"rxdma2host-monitor-destination-mac3",
41 	"rxdma2host-monitor-destination-mac2",
42 	"rxdma2host-monitor-destination-mac1",
43 	"ppdu-end-interrupts-mac3",
44 	"ppdu-end-interrupts-mac2",
45 	"ppdu-end-interrupts-mac1",
46 	"rxdma2host-monitor-status-ring-mac3",
47 	"rxdma2host-monitor-status-ring-mac2",
48 	"rxdma2host-monitor-status-ring-mac1",
49 	"host2rxdma-host-buf-ring-mac3",
50 	"host2rxdma-host-buf-ring-mac2",
51 	"host2rxdma-host-buf-ring-mac1",
52 	"rxdma2host-destination-ring-mac3",
53 	"rxdma2host-destination-ring-mac2",
54 	"rxdma2host-destination-ring-mac1",
55 	"host2tcl-input-ring4",
56 	"host2tcl-input-ring3",
57 	"host2tcl-input-ring2",
58 	"host2tcl-input-ring1",
59 	"wbm2host-tx-completions-ring3",
60 	"wbm2host-tx-completions-ring2",
61 	"wbm2host-tx-completions-ring1",
62 	"tcl2host-status-ring",
128 		if (msi_config->hw_rev == ab->hw_rev)  in ath11k_pcic_init_msi_config()
134 			   ab->hw_rev);  in ath11k_pcic_init_msi_config()
135 		return -EINVAL;  in ath11k_pcic_init_msi_config()
138 	ab->pci.msi.config = msi_config;  in ath11k_pcic_init_msi_config()
146 		iowrite32(value, ab->mem  + offset);  in __ath11k_pcic_write32()
148 		ab->pci.ops->window_write32(ab, offset, value);  in __ath11k_pcic_write32()
156 	/* for offset beyond BAR + 4K - 32, may  in ath11k_pcic_write32()
159 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&  in ath11k_pcic_write32()
161 	if (wakeup_required && ab->pci.ops->wakeup)  in ath11k_pcic_write32()
162 		ret = ab->pci.ops->wakeup(ab);  in ath11k_pcic_write32()
166 	if (wakeup_required && !ret && ab->pci.ops->release)  in ath11k_pcic_write32()
167 		ab->pci.ops->release(ab);  in ath11k_pcic_write32()
176 		val = ioread32(ab->mem + offset);  in __ath11k_pcic_read32()
178 		val = ab->pci.ops->window_read32(ab, offset);  in __ath11k_pcic_read32()
189 	/* for offset beyond BAR + 4K - 32, may  in ath11k_pcic_read32()
192 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&  in ath11k_pcic_read32()
194 	if (wakeup_required && ab->pci.ops->wakeup)  in ath11k_pcic_read32()
195 		ret = ab->pci.ops->wakeup(ab);  in ath11k_pcic_read32()
199 	if (wakeup_required && !ret && ab->pci.ops->release)  in ath11k_pcic_read32()
200 		ab->pci.ops->release(ab);  in ath11k_pcic_read32()
213 	/* for offset beyond BAR + 4K - 32, may  in ath11k_pcic_read()
216 	wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&  in ath11k_pcic_read()
218 	if (wakeup_required && ab->pci.ops->wakeup) {  in ath11k_pcic_read()
219 		ret = ab->pci.ops->wakeup(ab);  in ath11k_pcic_read()
237 	if (wakeup_required && ab->pci.ops->release)  in ath11k_pcic_read()
238 		ab->pci.ops->release(ab);  in ath11k_pcic_read()
247 	*msi_addr_lo = ab->pci.msi.addr_lo;  in ath11k_pcic_get_msi_address()
248 	*msi_addr_hi = ab->pci.msi.addr_hi;  in ath11k_pcic_get_msi_address()
256 	const struct ath11k_msi_config *msi_config = ab->pci.msi.config;  in ath11k_pcic_get_user_msi_assignment()
259 	for (idx = 0; idx < msi_config->total_users; idx++) {  in ath11k_pcic_get_user_msi_assignment()
260 		if (strcmp(user_name, msi_config->users[idx].name) == 0) {  in ath11k_pcic_get_user_msi_assignment()
261 			*num_vectors = msi_config->users[idx].num_vectors;  in ath11k_pcic_get_user_msi_assignment()
262 			*base_vector =  msi_config->users[idx].base_vector;  in ath11k_pcic_get_user_msi_assignment()
263 			*user_base_data = *base_vector + ab->pci.msi.ep_base_data;  in ath11k_pcic_get_user_msi_assignment()
276 	return -EINVAL;  in ath11k_pcic_get_user_msi_assignment()
284 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_get_ce_msi_idx()
302 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];  in ath11k_pcic_free_ext_irq()
304 		for (j = 0; j < irq_grp->num_irq; j++)  in ath11k_pcic_free_ext_irq()
305 			free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);  in ath11k_pcic_free_ext_irq()
307 		netif_napi_del(&irq_grp->napi);  in ath11k_pcic_free_ext_irq()
315 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_free_irq()
319 		free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);  in ath11k_pcic_free_irq()
333 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_ce_irq_enable()
337 	enable_irq(ab->irq_num[irq_idx]);  in ath11k_pcic_ce_irq_enable()
347 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_ce_irq_disable()
351 	disable_irq_nosync(ab->irq_num[irq_idx]);  in ath11k_pcic_ce_irq_disable()
358 	clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);  in ath11k_pcic_ce_irqs_disable()
360 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_ce_irqs_disable()
372 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_sync_ce_irqs()
377 		synchronize_irq(ab->irq_num[irq_idx]);  in ath11k_pcic_sync_ce_irqs()
384 	int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;  in ath11k_pcic_ce_tasklet()
386 	ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);  in ath11k_pcic_ce_tasklet()
388 	enable_irq(ce_pipe->ab->irq_num[irq_idx]);  in ath11k_pcic_ce_tasklet()
394 	struct ath11k_base *ab = ce_pipe->ab;  in ath11k_pcic_ce_interrupt_handler()
395 	int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;  in ath11k_pcic_ce_interrupt_handler()
397 	if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))  in ath11k_pcic_ce_interrupt_handler()
401 	ce_pipe->timestamp = jiffies;  in ath11k_pcic_ce_interrupt_handler()
403 	disable_irq_nosync(ab->irq_num[irq_idx]);  in ath11k_pcic_ce_interrupt_handler()
405 	tasklet_schedule(&ce_pipe->intr_tq);  in ath11k_pcic_ce_interrupt_handler()
412 	struct ath11k_base *ab = irq_grp->ab;  in ath11k_pcic_ext_grp_disable()
418 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_ext_grp_disable()
421 	for (i = 0; i < irq_grp->num_irq; i++)  in ath11k_pcic_ext_grp_disable()
422 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);  in ath11k_pcic_ext_grp_disable()
429 	clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &sc->dev_flags);  in __ath11k_pcic_ext_irq_disable()
432 		struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];  in __ath11k_pcic_ext_irq_disable()
436 		if (irq_grp->napi_enabled) {  in __ath11k_pcic_ext_irq_disable()
437 			napi_synchronize(&irq_grp->napi);  in __ath11k_pcic_ext_irq_disable()
438 			napi_disable(&irq_grp->napi);  in __ath11k_pcic_ext_irq_disable()
439 			irq_grp->napi_enabled = false;  in __ath11k_pcic_ext_irq_disable()
446 	struct ath11k_base *ab = irq_grp->ab;  in ath11k_pcic_ext_grp_enable()
452 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_ext_grp_enable()
455 	for (i = 0; i < irq_grp->num_irq; i++)  in ath11k_pcic_ext_grp_enable()
456 		enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);  in ath11k_pcic_ext_grp_enable()
464 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];  in ath11k_pcic_ext_irq_enable()
466 		if (!irq_grp->napi_enabled) {  in ath11k_pcic_ext_irq_enable()
467 			napi_enable(&irq_grp->napi);  in ath11k_pcic_ext_irq_enable()
468 			irq_grp->napi_enabled = true;  in ath11k_pcic_ext_irq_enable()
473 	set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);  in ath11k_pcic_ext_irq_enable()
482 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];  in ath11k_pcic_sync_ext_irqs()
484 		for (j = 0; j < irq_grp->num_irq; j++) {  in ath11k_pcic_sync_ext_irqs()
485 			irq_idx = irq_grp->irqs[j];  in ath11k_pcic_sync_ext_irqs()
486 			synchronize_irq(ab->irq_num[irq_idx]);  in ath11k_pcic_sync_ext_irqs()
503 	struct ath11k_base *ab = irq_grp->ab;  in ath11k_pcic_ext_grp_napi_poll()
510 		for (i = 0; i < irq_grp->num_irq; i++)  in ath11k_pcic_ext_grp_napi_poll()
511 			enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);  in ath11k_pcic_ext_grp_napi_poll()
523 	struct ath11k_base *ab = irq_grp->ab;  in ath11k_pcic_ext_interrupt_handler()
526 	if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))  in ath11k_pcic_ext_interrupt_handler()
529 	ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq);  in ath11k_pcic_ext_interrupt_handler()
532 	irq_grp->timestamp = jiffies;  in ath11k_pcic_ext_interrupt_handler()
534 	for (i = 0; i < irq_grp->num_irq; i++)  in ath11k_pcic_ext_interrupt_handler()
535 		disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);  in ath11k_pcic_ext_interrupt_handler()
537 	napi_schedule(&irq_grp->napi);  in ath11k_pcic_ext_interrupt_handler()
545 	return ab->pci.ops->get_msi_irq(ab, vector);  in ath11k_pcic_get_msi_irq()
561 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_ext_irq_config()
565 		struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];  in ath11k_pcic_ext_irq_config()
568 		irq_grp->ab = ab;  in ath11k_pcic_ext_irq_config()
569 		irq_grp->grp_id = i;  in ath11k_pcic_ext_irq_config()
570 		init_dummy_netdev(&irq_grp->napi_ndev);  in ath11k_pcic_ext_irq_config()
571 		netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,  in ath11k_pcic_ext_irq_config()
574 		if (ab->hw_params.ring_mask->tx[i] ||  in ath11k_pcic_ext_irq_config()
575 		    ab->hw_params.ring_mask->rx[i] ||  in ath11k_pcic_ext_irq_config()
576 		    ab->hw_params.ring_mask->rx_err[i] ||  in ath11k_pcic_ext_irq_config()
577 		    ab->hw_params.ring_mask->rx_wbm_rel[i] ||  in ath11k_pcic_ext_irq_config()
578 		    ab->hw_params.ring_mask->reo_status[i] ||  in ath11k_pcic_ext_irq_config()
579 		    ab->hw_params.ring_mask->rxdma2host[i] ||  in ath11k_pcic_ext_irq_config()
580 		    ab->hw_params.ring_mask->host2rxdma[i] ||  in ath11k_pcic_ext_irq_config()
581 		    ab->hw_params.ring_mask->rx_mon_status[i]) {  in ath11k_pcic_ext_irq_config()
585 		irq_grp->num_irq = num_irq;  in ath11k_pcic_ext_irq_config()
586 		irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i;  in ath11k_pcic_ext_irq_config()
588 		for (j = 0; j < irq_grp->num_irq; j++) {  in ath11k_pcic_ext_irq_config()
589 			int irq_idx = irq_grp->irqs[j];  in ath11k_pcic_ext_irq_config()
596 			ab->irq_num[irq_idx] = irq;  in ath11k_pcic_ext_irq_config()
632 	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))  in ath11k_pcic_config_irq()
636 	for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_config_irq()
645 		ce_pipe = &ab->ce.ce_pipe[i];  in ath11k_pcic_config_irq()
649 		tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet);  in ath11k_pcic_config_irq()
659 		ab->irq_num[irq_idx] = irq;  in ath11k_pcic_config_irq()
677 	set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);  in ath11k_pcic_ce_irqs_enable()
679 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_ce_irqs_enable()
691 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pcic_kill_tasklets()
692 		struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];  in ath11k_pcic_kill_tasklets()
697 		tasklet_kill(&ce_pipe->intr_tq);  in ath11k_pcic_kill_tasklets()
718 	set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);  in ath11k_pcic_start()
734 	for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {  in ath11k_pcic_map_service_to_pipe()
735 		entry = &ab->hw_params.svc_to_ce_map[i];  in ath11k_pcic_map_service_to_pipe()
737 		if (__le32_to_cpu(entry->service_id) != service_id)  in ath11k_pcic_map_service_to_pipe()
740 		switch (__le32_to_cpu(entry->pipedir)) {  in ath11k_pcic_map_service_to_pipe()
745 			*dl_pipe = __le32_to_cpu(entry->pipenum);  in ath11k_pcic_map_service_to_pipe()
750 			*ul_pipe = __le32_to_cpu(entry->pipenum);  in ath11k_pcic_map_service_to_pipe()
756 			*dl_pipe = __le32_to_cpu(entry->pipenum);  in ath11k_pcic_map_service_to_pipe()
757 			*ul_pipe = __le32_to_cpu(entry->pipenum);  in ath11k_pcic_map_service_to_pipe()
765 		return -ENOENT;  in ath11k_pcic_map_service_to_pipe()
778 	if (!pci_ops->get_msi_irq || !pci_ops->window_write32 ||  in ath11k_pcic_register_pci_ops()
779 	    !pci_ops->window_read32)  in ath11k_pcic_register_pci_ops()
780 		return -EINVAL;  in ath11k_pcic_register_pci_ops()
782 	ab->pci.ops = pci_ops;  in ath11k_pcic_register_pci_ops()
791 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pci_enable_ce_irqs_except_wake_irq()
806 	for (i = 0; i < ab->hw_params.ce_count; i++) {  in ath11k_pci_disable_ce_irqs_except_wake_irq()
807 		ce_pipe = &ab->ce.ce_pipe[i];  in ath11k_pci_disable_ce_irqs_except_wake_irq()
814 		disable_irq_nosync(ab->irq_num[irq_idx]);  in ath11k_pci_disable_ce_irqs_except_wake_irq()
815 		synchronize_irq(ab->irq_num[irq_idx]);  in ath11k_pci_disable_ce_irqs_except_wake_irq()
816 		tasklet_kill(&ce_pipe->intr_tq);  in ath11k_pci_disable_ce_irqs_except_wake_irq()