676 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)  in ath10k_pci_write32()  function
697 	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);  in ath10k_pci_soc_write32()
707 	ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);  in ath10k_pci_reg_write32()
729 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_disable_and_clear_legacy_irq()
731 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,  in ath10k_pci_disable_and_clear_legacy_irq()
743 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_enable_legacy_irq()
1567 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_set_ram_config()
1890 		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_mask()
1918 		ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +  in ath10k_pci_irq_msi_fw_unmask()
2274 	ath10k_pci_write32(ar, addr, val);  in ath10k_pci_wake_target_cpu()
2557 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);  in ath10k_pci_fw_crashed_clear()
2592 	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);  in ath10k_pci_warm_reset_cpu()
2956 	ath10k_pci_write32(ar,  in ath10k_pci_enable_eeprom()
2963 	ath10k_pci_write32(ar,  in ath10k_pci_enable_eeprom()
2969 	ath10k_pci_write32(ar,  in ath10k_pci_enable_eeprom()
2975 	ath10k_pci_write32(ar,  in ath10k_pci_enable_eeprom()
2995 	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);  in ath10k_pci_read_eeprom()
2998 	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,  in ath10k_pci_read_eeprom()
3022 	ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);  in ath10k_pci_read_eeprom()
3087 	.write32		= ath10k_pci_write32,
3254 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_init_irq()
3262 	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,  in ath10k_pci_deinit_irq_legacy()