net/wan/wanxlfw.S

197 	movel OR1, %d0
198 	andl #0xF00007FF, %d0		// mask AMxx bits
199 	orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
200 	movel %d0, OR1
204 	clrl %d0			// D0 = 4 * port
205 init_1:	tstl ch_status_addr(%d0)
207 	addl #VALUE_WINDOW, ch_status_addr(%d0)
208 init_2:	addl #4, %d0
209 	cmpl #4 * 4, %d0
258 main_1:	clrl %d0			// D0 = 4 * port
281 	addl #4, %d0			// D0 = 4 * next port
282 	cmpl #4 * 4, %d0
291 	movel ch_status_addr(%d0), %a0	// A0 = port status address
296 	clrl tx_in(%d0)
297 	clrl tx_out(%d0)
298 	clrl tx_count(%d0)
299 	clrl rx_in(%d0)
302 	andl clocking_mask(%d0), %d1
305 	orl clocking_txfromrx(%d0), %d1
309 	orl clocking_ext(%d0), %d1
313 	orw #STATUS_CABLE_DTR, csr_output(%d0)	// DTR on
317 	movel first_buffer(%d0), %d1	// D1 = starting buffer address
318 	movel tx_first_bd(%d0), %a1	// A1 = starting TX BD address
346 	movel scc_base_addr(%d0), %a1	// A1 = SCC_BASE address
347 	movel scc_reg_addr(%d0), %a2	// A2 = SCC_REGS address
352 	movel tx_first_bd(%d0), %d1
366 	movew #2, parity_bytes(%d0)
376 	movew #4, parity_bytes(%d0)
386 	movew #2, parity_bytes(%d0)
396 	movew #4, parity_bytes(%d0)
404 	clrw parity_bytes(%d0)
417 	movel %d0, %d1
433 	movel scc_reg_addr(%d0), %a0	// A0 = SCC_REGS address
437 	andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off
440 	movel ch_status_addr(%d0), %d1
448 	cmpl #TX_BUFFERS, tx_count(%d0)
451 	movel tx_out(%d0), %d1
454 	addl ch_status_addr(%d0), %d2
462 	addl tx_first_bd(%d0), %d1	// D1 = current tx_out BD addr
471 	movel tx_out(%d0), %d1
476 tx_1:	movel %d1, tx_out(%d0)
478 	addl #1, tx_count(%d0)
487 rx:	movel rx_in(%d0), %d1		// D1 = rx_in BD#
489 	addl rx_first_bd(%d0), %d1	// D1 = current rx_in BD address
497 	tstw parity_bytes(%d0)
506 	subw parity_bytes(%d0), %d3	// D3 = packet length
524 	movel packet_full(%d0), (%d2)	// update desc stat
539 	movel rx_in(%d0), %d1
544 rx_2:	movel %d1, rx_in(%d0)
548 	movel ch_status_addr(%d0), %d2
553 	movel ch_status_addr(%d0), %d2
563 tx_end:	tstl tx_count(%d0)
566 	movel tx_in(%d0), %d1
569 	addl tx_first_bd(%d0), %d1	// D1 = current tx_in BD address
575 	orl bell_tx(%d0), %d6		// signal host that TX desc freed
576 	subl #1, tx_count(%d0)
577 	movel tx_in(%d0), %d1
583 	movel %d1, tx_in(%d0)
587 	addl ch_status_addr(%d0), %d2
606 	movel %d0, -(%sp)
609 	movel PLX_DMA_CMD_STS, %d0	// do not btst PLX register directly
610 	btstl #4, %d0			// transfer done?
617 	movel %d0, -(%sp)
620 	movel PLX_DMA_CMD_STS, %d0	// do not btst PLX register directly
621 	btstl #12, %d0			// transfer done?
629 	movel (%sp)+, %d0
641 	movel %d0, -(%sp)
643 	movel PLX_DOORBELL_TO_CARD, %d0
644 	movel %d0, PLX_DOORBELL_TO_CARD	// confirm all requests
645 	orl %d0, channel_stats
649 	movel (%sp)+, %d0
685 	movel %d0, -(%sp)
691 	clrl %d0			// D0 = 4 * port
726 	movew csr_output(%d0), %d2
732 	cmpw old_csr_output(%d0), %d1
734 	movew %d1, old_csr_output(%d0)
739 	andw dcd_mask(%d0), %d1
750 	movel ch_status_addr(%d0), %a1
754 	movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD	// signal the host
758 	addl #4, %d0			// D0 = 4 * next port
759 	cmpl #4 * 4, %d0
766 	movel (%sp)+, %d0
782 	movel #128 * 1024, %d0		// D0 = RAM size tested
784 	cmpl #MAX_RAM_SIZE, %d0
786 	movel %d0, %a0
791 	lsll #1, %d0
801 	movel %d0, %a0			// A0 = fill ptr
802 	subl #firmware_end + 4, %d0
803 	lsrl #2, %d0
804 	movel %d0, %d1			// D1 = DBf counter
814 	dbnew %d0, ram_test_loop
816 	subl #0x10000, %d0
817 	cmpl #0xFFFFFFFF, %d0