Lines Matching defs:chan
46 #define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ argument
47 #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ argument
48 #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ argument
49 #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ argument
50 #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ argument
51 #define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ argument
52 #define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */ argument
53 #define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ argument
54 #define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */ argument
126 #define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */ argument
127 #define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */ argument
128 #define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */ argument
129 #define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */ argument
130 #define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */ argument
131 #define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */ argument
132 #define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */ argument
133 #define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */ argument
134 #define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */ argument
135 #define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */ argument