Lines Matching +full:tdm +full:- +full:sync +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/dma-mapping.h>
54 .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
93 ut_info = priv->ut_info; in uhdlc_init()
94 uf_info = &ut_info->uf_info; in uhdlc_init()
96 if (priv->tsa) { in uhdlc_init()
97 uf_info->tsa = 1; in uhdlc_init()
98 uf_info->ctsp = 1; in uhdlc_init()
99 uf_info->cds = 1; in uhdlc_init()
100 uf_info->ctss = 1; in uhdlc_init()
102 uf_info->cds = 0; in uhdlc_init()
103 uf_info->ctsp = 0; in uhdlc_init()
104 uf_info->ctss = 0; in uhdlc_init()
110 if (priv->hdlc_bus) in uhdlc_init()
111 uf_info->brkpt_support = 1; in uhdlc_init()
113 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF | in uhdlc_init()
116 ret = ucc_fast_init(uf_info, &priv->uccf); in uhdlc_init()
118 dev_err(priv->dev, "Failed to init uccf."); in uhdlc_init()
122 priv->uf_regs = priv->uccf->uf_regs; in uhdlc_init()
123 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_init()
125 /* Loopback mode */ in uhdlc_init()
126 if (priv->loopback) { in uhdlc_init()
127 dev_info(priv->dev, "Loopback Mode\n"); in uhdlc_init()
129 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1); in uhdlc_init()
131 gumr = ioread32be(&priv->uf_regs->gumr); in uhdlc_init()
135 iowrite32be(gumr, &priv->uf_regs->gumr); in uhdlc_init()
139 if (priv->tsa) in uhdlc_init()
140 ucc_tdm_init(priv->utdm, priv->ut_info); in uhdlc_init()
143 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); in uhdlc_init()
147 /* Set UPSMR normal mode (need fixed)*/ in uhdlc_init()
148 iowrite32be(0, &priv->uf_regs->upsmr); in uhdlc_init()
150 /* hdlc_bus mode */ in uhdlc_init()
151 if (priv->hdlc_bus) { in uhdlc_init()
154 dev_info(priv->dev, "HDLC bus Mode\n"); in uhdlc_init()
155 upsmr = ioread32be(&priv->uf_regs->upsmr); in uhdlc_init()
157 /* bus mode and retransmit enable, with collision window in uhdlc_init()
162 iowrite32be(upsmr, &priv->uf_regs->upsmr); in uhdlc_init()
165 gumr = ioread32be(&priv->uf_regs->gumr); in uhdlc_init()
167 /* set automatic sync to explicitly ignore CD signal */ in uhdlc_init()
169 iowrite32be(gumr, &priv->uf_regs->gumr); in uhdlc_init()
172 priv->rx_ring_size = RX_BD_RING_LEN; in uhdlc_init()
173 priv->tx_ring_size = TX_BD_RING_LEN; in uhdlc_init()
175 priv->rx_bd_base = dma_alloc_coherent(priv->dev, in uhdlc_init()
177 &priv->dma_rx_bd, GFP_KERNEL); in uhdlc_init()
179 if (!priv->rx_bd_base) { in uhdlc_init()
180 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n"); in uhdlc_init()
181 ret = -ENOMEM; in uhdlc_init()
186 priv->tx_bd_base = dma_alloc_coherent(priv->dev, in uhdlc_init()
188 &priv->dma_tx_bd, GFP_KERNEL); in uhdlc_init()
190 if (!priv->tx_bd_base) { in uhdlc_init()
191 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n"); in uhdlc_init()
192 ret = -ENOMEM; in uhdlc_init()
197 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param), in uhdlc_init()
200 if (priv->ucc_pram_offset < 0) { in uhdlc_init()
201 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n"); in uhdlc_init()
202 ret = -ENOMEM; in uhdlc_init()
206 priv->rx_skbuff = kcalloc(priv->rx_ring_size, in uhdlc_init()
207 sizeof(*priv->rx_skbuff), in uhdlc_init()
209 if (!priv->rx_skbuff) { in uhdlc_init()
210 ret = -ENOMEM; in uhdlc_init()
214 priv->tx_skbuff = kcalloc(priv->tx_ring_size, in uhdlc_init()
215 sizeof(*priv->tx_skbuff), in uhdlc_init()
217 if (!priv->tx_skbuff) { in uhdlc_init()
218 ret = -ENOMEM; in uhdlc_init()
222 priv->skb_curtx = 0; in uhdlc_init()
223 priv->skb_dirtytx = 0; in uhdlc_init()
224 priv->curtx_bd = priv->tx_bd_base; in uhdlc_init()
225 priv->dirty_tx = priv->tx_bd_base; in uhdlc_init()
226 priv->currx_bd = priv->rx_bd_base; in uhdlc_init()
227 priv->currx_bdnum = 0; in uhdlc_init()
230 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); in uhdlc_init()
232 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); in uhdlc_init()
234 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) in uhdlc_init()
235 qe_muram_addr(priv->ucc_pram_offset); in uhdlc_init()
238 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param)); in uhdlc_init()
243 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n"); in uhdlc_init()
244 ret = -ENOMEM; in uhdlc_init()
250 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n"); in uhdlc_init()
251 ret = -ENOMEM; in uhdlc_init()
255 dev_err(priv->dev, "MURAM allocation out of addressable range\n"); in uhdlc_init()
256 ret = -ENOMEM; in uhdlc_init()
261 iowrite16be(riptr, &priv->ucc_pram->riptr); in uhdlc_init()
262 iowrite16be(tiptr, &priv->ucc_pram->tiptr); in uhdlc_init()
265 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr); in uhdlc_init()
268 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase); in uhdlc_init()
269 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase); in uhdlc_init()
272 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate); in uhdlc_init()
273 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate); in uhdlc_init()
276 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask); in uhdlc_init()
277 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres); in uhdlc_init()
279 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr); in uhdlc_init()
280 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr); in uhdlc_init()
281 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt); in uhdlc_init()
282 iowrite16be(priv->hmask, &priv->ucc_pram->hmask); in uhdlc_init()
283 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1); in uhdlc_init()
284 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2); in uhdlc_init()
285 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3); in uhdlc_init()
286 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4); in uhdlc_init()
289 bd_buffer = dma_alloc_coherent(priv->dev, in uhdlc_init()
294 dev_err(priv->dev, "Could not allocate buffer descriptors\n"); in uhdlc_init()
295 ret = -ENOMEM; in uhdlc_init()
299 priv->rx_buffer = bd_buffer; in uhdlc_init()
300 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; in uhdlc_init()
302 priv->dma_rx_addr = bd_dma_addr; in uhdlc_init()
303 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; in uhdlc_init()
306 if (i < (RX_BD_RING_LEN - 1)) in uhdlc_init()
311 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); in uhdlc_init()
312 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); in uhdlc_init()
316 if (i < (TX_BD_RING_LEN - 1)) in uhdlc_init()
321 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); in uhdlc_init()
322 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); in uhdlc_init()
333 kfree(priv->tx_skbuff); in uhdlc_init()
335 kfree(priv->rx_skbuff); in uhdlc_init()
337 qe_muram_free(priv->ucc_pram_offset); in uhdlc_init()
339 dma_free_coherent(priv->dev, in uhdlc_init()
341 priv->tx_bd_base, priv->dma_tx_bd); in uhdlc_init()
343 dma_free_coherent(priv->dev, in uhdlc_init()
345 priv->rx_bd_base, priv->dma_rx_bd); in uhdlc_init()
347 ucc_fast_free(priv->uccf); in uhdlc_init()
355 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv; in ucc_hdlc_tx()
361 switch (dev->type) { in ucc_hdlc_tx()
364 dev->stats.tx_dropped++; in ucc_hdlc_tx()
367 return -ENOMEM; in ucc_hdlc_tx()
372 proto_head = (__be16 *)skb->data; in ucc_hdlc_tx()
375 dev->stats.tx_bytes += skb->len; in ucc_hdlc_tx()
379 proto_head = (__be16 *)skb->data; in ucc_hdlc_tx()
381 dev->stats.tx_dropped++; in ucc_hdlc_tx()
384 return -ENOMEM; in ucc_hdlc_tx()
387 dev->stats.tx_bytes += skb->len; in ucc_hdlc_tx()
391 dev->stats.tx_bytes += skb->len; in ucc_hdlc_tx()
395 dev->stats.tx_dropped++; in ucc_hdlc_tx()
397 return -ENOMEM; in ucc_hdlc_tx()
399 netdev_sent_queue(dev, skb->len); in ucc_hdlc_tx()
400 spin_lock_irqsave(&priv->lock, flags); in ucc_hdlc_tx()
404 bd = priv->curtx_bd; in ucc_hdlc_tx()
405 bd_status = be16_to_cpu(bd->status); in ucc_hdlc_tx()
407 priv->tx_skbuff[priv->skb_curtx] = skb; in ucc_hdlc_tx()
410 priv->skb_curtx = in ucc_hdlc_tx()
411 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); in ucc_hdlc_tx()
414 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr), in ucc_hdlc_tx()
415 skb->data, skb->len); in ucc_hdlc_tx()
420 bd->length = cpu_to_be16(skb->len); in ucc_hdlc_tx()
421 bd->status = cpu_to_be16(bd_status); in ucc_hdlc_tx()
427 bd = priv->tx_bd_base; in ucc_hdlc_tx()
429 if (bd == priv->dirty_tx) { in ucc_hdlc_tx()
434 priv->curtx_bd = bd; in ucc_hdlc_tx()
436 spin_unlock_irqrestore(&priv->lock, flags); in ucc_hdlc_tx()
446 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num); in hdlc_tx_restart()
456 struct net_device *dev = priv->ndev; in hdlc_tx_done()
464 bd = priv->dirty_tx; in hdlc_tx_done()
465 bd_status = be16_to_cpu(bd->status); in hdlc_tx_done()
472 dev->stats.tx_fifo_errors++; in hdlc_tx_done()
476 dev->stats.tx_carrier_errors++; in hdlc_tx_done()
484 skb = priv->tx_skbuff[priv->skb_dirtytx]; in hdlc_tx_done()
488 bytes_sent += skb->len; in hdlc_tx_done()
489 dev->stats.tx_packets++; in hdlc_tx_done()
490 memset(priv->tx_buffer + in hdlc_tx_done()
491 (be32_to_cpu(bd->buf) - priv->dma_tx_addr), in hdlc_tx_done()
492 0, skb->len); in hdlc_tx_done()
495 priv->tx_skbuff[priv->skb_dirtytx] = NULL; in hdlc_tx_done()
496 priv->skb_dirtytx = in hdlc_tx_done()
497 (priv->skb_dirtytx + in hdlc_tx_done()
508 bd = priv->tx_bd_base; in hdlc_tx_done()
509 bd_status = be16_to_cpu(bd->status); in hdlc_tx_done()
511 priv->dirty_tx = bd; in hdlc_tx_done()
522 struct net_device *dev = priv->ndev; in hdlc_rx_done()
531 bd = priv->currx_bd; in hdlc_rx_done()
532 bd_status = be16_to_cpu(bd->status); in hdlc_rx_done()
535 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) { in hdlc_rx_done()
537 dev->stats.rx_errors++; in hdlc_rx_done()
540 dev->stats.collisions++; in hdlc_rx_done()
542 dev->stats.rx_fifo_errors++; in hdlc_rx_done()
544 dev->stats.rx_crc_errors++; in hdlc_rx_done()
546 dev->stats.rx_over_errors++; in hdlc_rx_done()
548 dev->stats.rx_frame_errors++; in hdlc_rx_done()
550 dev->stats.rx_length_errors++; in hdlc_rx_done()
554 bdbuffer = priv->rx_buffer + in hdlc_rx_done()
555 (priv->currx_bdnum * MAX_RX_BUF_LENGTH); in hdlc_rx_done()
556 length = be16_to_cpu(bd->length); in hdlc_rx_done()
558 switch (dev->type) { in hdlc_rx_done()
561 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE); in hdlc_rx_done()
565 dev->stats.rx_dropped++; in hdlc_rx_done()
566 return -ENOMEM; in hdlc_rx_done()
570 skb->len = length; in hdlc_rx_done()
571 skb->dev = dev; in hdlc_rx_done()
572 memcpy(skb->data, bdbuffer, length); in hdlc_rx_done()
577 length -= HDLC_CRC_SIZE; in hdlc_rx_done()
581 dev->stats.rx_dropped++; in hdlc_rx_done()
582 return -ENOMEM; in hdlc_rx_done()
586 skb->len = length; in hdlc_rx_done()
587 skb->dev = dev; in hdlc_rx_done()
588 memcpy(skb->data, bdbuffer, length); in hdlc_rx_done()
592 dev->stats.rx_packets++; in hdlc_rx_done()
593 dev->stats.rx_bytes += skb->len; in hdlc_rx_done()
595 if (hdlc->proto) in hdlc_rx_done()
596 skb->protocol = hdlc_type_trans(skb, dev); in hdlc_rx_done()
600 bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S); in hdlc_rx_done()
604 priv->currx_bdnum = 0; in hdlc_rx_done()
605 bd = priv->rx_bd_base; in hdlc_rx_done()
607 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1)) in hdlc_rx_done()
608 priv->currx_bdnum += 1; in hdlc_rx_done()
610 priv->currx_bdnum = RX_BD_RING_LEN - 1; in hdlc_rx_done()
615 bd_status = be16_to_cpu(bd->status); in hdlc_rx_done()
619 priv->currx_bd = bd; in hdlc_rx_done()
631 spin_lock(&priv->lock); in ucc_hdlc_poll()
633 spin_unlock(&priv->lock); in ucc_hdlc_poll()
636 howmany += hdlc_rx_done(priv, budget - howmany); in ucc_hdlc_poll()
640 qe_setbits_be32(priv->uccf->p_uccm, in ucc_hdlc_poll()
650 struct net_device *dev = priv->ndev; in ucc_hdlc_irq_handler()
655 uccf = priv->uccf; in ucc_hdlc_irq_handler()
657 ucce = ioread32be(uccf->p_ucce); in ucc_hdlc_irq_handler()
658 uccm = ioread32be(uccf->p_uccm); in ucc_hdlc_irq_handler()
660 iowrite32be(ucce, uccf->p_ucce); in ucc_hdlc_irq_handler()
665 if (napi_schedule_prep(&priv->napi)) { in ucc_hdlc_irq_handler()
668 iowrite32be(uccm, uccf->p_uccm); in ucc_hdlc_irq_handler()
669 __napi_schedule(&priv->napi); in ucc_hdlc_irq_handler()
675 dev->stats.rx_missed_errors++; in ucc_hdlc_irq_handler()
677 dev->stats.tx_errors++; in ucc_hdlc_irq_handler()
688 switch (ifs->type) { in uhdlc_ioctl()
690 ifs->type = IF_IFACE_E1; in uhdlc_ioctl()
691 if (ifs->size < size) { in uhdlc_ioctl()
692 ifs->size = size; /* data size wanted */ in uhdlc_ioctl()
693 return -ENOBUFS; in uhdlc_ioctl()
696 line.clock_type = priv->clocking; in uhdlc_ioctl()
698 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size)) in uhdlc_ioctl()
699 return -EFAULT; in uhdlc_ioctl()
711 struct ucc_hdlc_private *priv = hdlc->priv; in uhdlc_open()
712 struct ucc_tdm *utdm = priv->utdm; in uhdlc_open()
715 if (priv->hdlc_busy != 1) { in uhdlc_open()
716 if (request_irq(priv->ut_info->uf_info.irq, in uhdlc_open()
718 return -ENODEV; in uhdlc_open()
721 priv->ut_info->uf_info.ucc_num); in uhdlc_open()
726 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_open()
728 /* Enable the TDM port */ in uhdlc_open()
729 if (priv->tsa) in uhdlc_open()
730 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); in uhdlc_open()
732 priv->hdlc_busy = 1; in uhdlc_open()
733 netif_device_attach(priv->ndev); in uhdlc_open()
734 napi_enable(&priv->napi); in uhdlc_open()
748 qe_muram_free(ioread16be(&priv->ucc_pram->riptr)); in uhdlc_memclean()
749 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr)); in uhdlc_memclean()
751 if (priv->rx_bd_base) { in uhdlc_memclean()
752 dma_free_coherent(priv->dev, in uhdlc_memclean()
754 priv->rx_bd_base, priv->dma_rx_bd); in uhdlc_memclean()
756 priv->rx_bd_base = NULL; in uhdlc_memclean()
757 priv->dma_rx_bd = 0; in uhdlc_memclean()
760 if (priv->tx_bd_base) { in uhdlc_memclean()
761 dma_free_coherent(priv->dev, in uhdlc_memclean()
763 priv->tx_bd_base, priv->dma_tx_bd); in uhdlc_memclean()
765 priv->tx_bd_base = NULL; in uhdlc_memclean()
766 priv->dma_tx_bd = 0; in uhdlc_memclean()
769 if (priv->ucc_pram) { in uhdlc_memclean()
770 qe_muram_free(priv->ucc_pram_offset); in uhdlc_memclean()
771 priv->ucc_pram = NULL; in uhdlc_memclean()
772 priv->ucc_pram_offset = 0; in uhdlc_memclean()
775 kfree(priv->rx_skbuff); in uhdlc_memclean()
776 priv->rx_skbuff = NULL; in uhdlc_memclean()
778 kfree(priv->tx_skbuff); in uhdlc_memclean()
779 priv->tx_skbuff = NULL; in uhdlc_memclean()
781 if (priv->uf_regs) { in uhdlc_memclean()
782 iounmap(priv->uf_regs); in uhdlc_memclean()
783 priv->uf_regs = NULL; in uhdlc_memclean()
786 if (priv->uccf) { in uhdlc_memclean()
787 ucc_fast_free(priv->uccf); in uhdlc_memclean()
788 priv->uccf = NULL; in uhdlc_memclean()
791 if (priv->rx_buffer) { in uhdlc_memclean()
792 dma_free_coherent(priv->dev, in uhdlc_memclean()
794 priv->rx_buffer, priv->dma_rx_addr); in uhdlc_memclean()
795 priv->rx_buffer = NULL; in uhdlc_memclean()
796 priv->dma_rx_addr = 0; in uhdlc_memclean()
799 if (priv->tx_buffer) { in uhdlc_memclean()
800 dma_free_coherent(priv->dev, in uhdlc_memclean()
802 priv->tx_buffer, priv->dma_tx_addr); in uhdlc_memclean()
803 priv->tx_buffer = NULL; in uhdlc_memclean()
804 priv->dma_tx_addr = 0; in uhdlc_memclean()
810 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; in uhdlc_close()
811 struct ucc_tdm *utdm = priv->utdm; in uhdlc_close()
814 napi_disable(&priv->napi); in uhdlc_close()
816 priv->ut_info->uf_info.ucc_num); in uhdlc_close()
823 if (priv->tsa) in uhdlc_close()
824 qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); in uhdlc_close()
826 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_close()
828 free_irq(priv->ut_info->uf_info.irq, priv); in uhdlc_close()
831 priv->hdlc_busy = 0; in uhdlc_close()
841 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; in ucc_hdlc_attach()
845 return -EINVAL; in ucc_hdlc_attach()
851 return -EINVAL; in ucc_hdlc_attach()
853 priv->encoding = encoding; in ucc_hdlc_attach()
854 priv->parity = parity; in ucc_hdlc_attach()
862 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; in store_clk_config()
865 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h); in store_clk_config()
866 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l); in store_clk_config()
868 /* store si sync */ in store_clk_config()
869 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr); in store_clk_config()
872 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32)); in store_clk_config()
877 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; in resume_clk_config()
879 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32)); in resume_clk_config()
881 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h); in resume_clk_config()
882 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l); in resume_clk_config()
884 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr); in resume_clk_config()
893 return -EINVAL; in uhdlc_suspend()
895 if (!netif_running(priv->ndev)) in uhdlc_suspend()
898 netif_device_detach(priv->ndev); in uhdlc_suspend()
899 napi_disable(&priv->napi); in uhdlc_suspend()
901 uf_regs = priv->uf_regs; in uhdlc_suspend()
904 priv->gumr = ioread32be(&uf_regs->gumr); in uhdlc_suspend()
905 priv->guemr = ioread8(&uf_regs->guemr); in uhdlc_suspend()
907 priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak), in uhdlc_suspend()
909 if (!priv->ucc_pram_bak) in uhdlc_suspend()
910 return -ENOMEM; in uhdlc_suspend()
913 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram, in uhdlc_suspend()
920 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_suspend()
938 return -EINVAL; in uhdlc_resume()
940 if (!netif_running(priv->ndev)) in uhdlc_resume()
943 utdm = priv->utdm; in uhdlc_resume()
944 ut_info = priv->ut_info; in uhdlc_resume()
945 uf_info = &ut_info->uf_info; in uhdlc_resume()
946 uf_regs = priv->uf_regs; in uhdlc_resume()
947 uccf = priv->uccf; in uhdlc_resume()
950 iowrite8(priv->guemr, &uf_regs->guemr); in uhdlc_resume()
951 iowrite32be(priv->gumr, &uf_regs->gumr); in uhdlc_resume()
954 iowrite16be(uf_info->urfs, &uf_regs->urfs); in uhdlc_resume()
955 iowrite16be(uf_info->urfet, &uf_regs->urfet); in uhdlc_resume()
956 iowrite16be(uf_info->urfset, &uf_regs->urfset); in uhdlc_resume()
957 iowrite16be(uf_info->utfs, &uf_regs->utfs); in uhdlc_resume()
958 iowrite16be(uf_info->utfet, &uf_regs->utfet); in uhdlc_resume()
959 iowrite16be(uf_info->utftt, &uf_regs->utftt); in uhdlc_resume()
961 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb); in uhdlc_resume()
962 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb); in uhdlc_resume()
964 /* Rx Tx and sync clock routing */ in uhdlc_resume()
967 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm); in uhdlc_resume()
968 iowrite32be(0xffffffff, &uf_regs->ucce); in uhdlc_resume()
970 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_resume()
973 if (priv->tsa) in uhdlc_resume()
974 ucc_tdm_init(priv->utdm, priv->ut_info); in uhdlc_resume()
977 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); in uhdlc_resume()
981 /* Set UPSMR normal mode */ in uhdlc_resume()
982 iowrite32be(0, &uf_regs->upsmr); in uhdlc_resume()
985 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); in uhdlc_resume()
987 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); in uhdlc_resume()
989 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) in uhdlc_resume()
990 qe_muram_addr(priv->ucc_pram_offset); in uhdlc_resume()
993 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak, in uhdlc_resume()
995 kfree(priv->ucc_pram_bak); in uhdlc_resume()
999 if (i < (RX_BD_RING_LEN - 1)) in uhdlc_resume()
1004 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); in uhdlc_resume()
1005 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); in uhdlc_resume()
1009 if (i < (TX_BD_RING_LEN - 1)) in uhdlc_resume()
1014 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); in uhdlc_resume()
1015 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); in uhdlc_resume()
1020 if (priv->hdlc_busy == 1) { in uhdlc_resume()
1022 priv->ut_info->uf_info.ucc_num); in uhdlc_resume()
1027 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); in uhdlc_resume()
1029 /* Enable the TDM port */ in uhdlc_resume()
1030 if (priv->tsa) in uhdlc_resume()
1031 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); in uhdlc_resume()
1034 napi_enable(&priv->napi); in uhdlc_resume()
1035 netif_device_attach(priv->ndev); in uhdlc_resume()
1077 return -EINVAL; in hdlc_map_iomem()
1083 return -EINVAL; in hdlc_map_iomem()
1089 ret = -EINVAL; in hdlc_map_iomem()
1092 *ptr = ioremap(res->start, resource_size(res)); in hdlc_map_iomem()
1094 ret = -ENOMEM; in hdlc_map_iomem()
1101 put_device(&pdev->dev); in hdlc_map_iomem()
1110 put_device(&pdev->dev); in hdlc_map_iomem()
1117 struct device_node *np = pdev->dev.of_node; in ucc_hdlc_probe()
1129 ret = of_property_read_u32_index(np, "cell-index", 0, &val); in ucc_hdlc_probe()
1131 dev_err(&pdev->dev, "Invalid ucc property\n"); in ucc_hdlc_probe()
1132 return -ENODEV; in ucc_hdlc_probe()
1135 ucc_num = val - 1; in ucc_hdlc_probe()
1136 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) { in ucc_hdlc_probe()
1137 dev_err(&pdev->dev, ": Invalid UCC num\n"); in ucc_hdlc_probe()
1138 return -EINVAL; in ucc_hdlc_probe()
1145 ut_info->uf_info.ucc_num = ucc_num; in ucc_hdlc_probe()
1147 sprop = of_get_property(np, "rx-clock-name", NULL); in ucc_hdlc_probe()
1149 ut_info->uf_info.rx_clock = qe_clock_source(sprop); in ucc_hdlc_probe()
1150 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) || in ucc_hdlc_probe()
1151 (ut_info->uf_info.rx_clock > QE_CLK24)) { in ucc_hdlc_probe()
1152 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); in ucc_hdlc_probe()
1153 return -EINVAL; in ucc_hdlc_probe()
1156 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); in ucc_hdlc_probe()
1157 return -EINVAL; in ucc_hdlc_probe()
1160 sprop = of_get_property(np, "tx-clock-name", NULL); in ucc_hdlc_probe()
1162 ut_info->uf_info.tx_clock = qe_clock_source(sprop); in ucc_hdlc_probe()
1163 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) || in ucc_hdlc_probe()
1164 (ut_info->uf_info.tx_clock > QE_CLK24)) { in ucc_hdlc_probe()
1165 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); in ucc_hdlc_probe()
1166 return -EINVAL; in ucc_hdlc_probe()
1169 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); in ucc_hdlc_probe()
1170 return -EINVAL; in ucc_hdlc_probe()
1175 return -EINVAL; in ucc_hdlc_probe()
1177 ut_info->uf_info.regs = res.start; in ucc_hdlc_probe()
1178 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0); in ucc_hdlc_probe()
1182 return -ENOMEM; in ucc_hdlc_probe()
1184 dev_set_drvdata(&pdev->dev, uhdlc_priv); in ucc_hdlc_probe()
1185 uhdlc_priv->dev = &pdev->dev; in ucc_hdlc_probe()
1186 uhdlc_priv->ut_info = ut_info; in ucc_hdlc_probe()
1188 uhdlc_priv->tsa = of_property_read_bool(np, "fsl,tdm-interface"); in ucc_hdlc_probe()
1189 uhdlc_priv->loopback = of_property_read_bool(np, "fsl,ucc-internal-loopback"); in ucc_hdlc_probe()
1190 uhdlc_priv->hdlc_bus = of_property_read_bool(np, "fsl,hdlc-bus"); in ucc_hdlc_probe()
1192 if (uhdlc_priv->tsa == 1) { in ucc_hdlc_probe()
1195 ret = -ENOMEM; in ucc_hdlc_probe()
1196 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n"); in ucc_hdlc_probe()
1199 uhdlc_priv->utdm = utdm; in ucc_hdlc_probe()
1204 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0, in ucc_hdlc_probe()
1205 (void __iomem **)&utdm->si_regs); in ucc_hdlc_probe()
1208 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1, in ucc_hdlc_probe()
1209 (void __iomem **)&utdm->siram); in ucc_hdlc_probe()
1214 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask)) in ucc_hdlc_probe()
1215 uhdlc_priv->hmask = DEFAULT_ADDR_MASK; in ucc_hdlc_probe()
1219 dev_err(&pdev->dev, "Failed to init uhdlc\n"); in ucc_hdlc_probe()
1225 ret = -ENOMEM; in ucc_hdlc_probe()
1230 uhdlc_priv->ndev = dev; in ucc_hdlc_probe()
1232 dev->tx_queue_len = 16; in ucc_hdlc_probe()
1233 dev->netdev_ops = &uhdlc_ops; in ucc_hdlc_probe()
1234 dev->watchdog_timeo = 2 * HZ; in ucc_hdlc_probe()
1235 hdlc->attach = ucc_hdlc_attach; in ucc_hdlc_probe()
1236 hdlc->xmit = ucc_hdlc_tx; in ucc_hdlc_probe()
1237 netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32); in ucc_hdlc_probe()
1239 ret = -ENOBUFS; in ucc_hdlc_probe()
1250 iounmap(utdm->siram); in ucc_hdlc_probe()
1253 iounmap(utdm->si_regs); in ucc_hdlc_probe()
1255 if (uhdlc_priv->tsa) in ucc_hdlc_probe()
1264 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev); in ucc_hdlc_remove()
1268 if (priv->utdm->si_regs) { in ucc_hdlc_remove()
1269 iounmap(priv->utdm->si_regs); in ucc_hdlc_remove()
1270 priv->utdm->si_regs = NULL; in ucc_hdlc_remove()
1273 if (priv->utdm->siram) { in ucc_hdlc_remove()
1274 iounmap(priv->utdm->siram); in ucc_hdlc_remove()
1275 priv->utdm->siram = NULL; in ucc_hdlc_remove()
1279 dev_info(&pdev->dev, "UCC based hdlc module removed\n"); in ucc_hdlc_remove()
1286 .compatible = "fsl,ucc-hdlc",