Lines Matching refs:vsc85xx_ts_write_csr
106 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk, in vsc85xx_ts_write_csr() function
195 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i), in vsc85xx_ts_fsb_init()
199 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3), in vsc85xx_ts_fsb_init()
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY, in vsc85xx_ts_set_latencies()
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in vsc85xx_ts_set_latencies()
283 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY, in vsc85xx_ts_set_latencies()
288 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in vsc85xx_ts_set_latencies()
295 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
298 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM, in vsc85xx_ts_disable_flows()
301 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0); in vsc85xx_ts_disable_flows()
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0); in vsc85xx_ts_disable_flows()
306 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
308 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
310 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
312 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
314 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i), in vsc85xx_ts_disable_flows()
320 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0); in vsc85xx_ts_disable_flows()
321 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
323 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
325 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
327 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
329 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
331 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
333 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
335 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_disable_flows()
337 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i), in vsc85xx_ts_disable_flows()
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_ts_eth_cmp1_sig()
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val); in vsc85xx_ts_eth_cmp1_sig()
517 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_cmp_init()
524 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
527 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
531 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ptp_cmp_init()
545 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0); in vsc85xx_eth_cmp1_init()
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID, in vsc85xx_eth_cmp1_init()
549 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), in vsc85xx_eth_cmp1_init()
551 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
553 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0); in vsc85xx_eth_cmp1_init()
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0); in vsc85xx_eth_cmp1_init()
555 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
557 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0); in vsc85xx_eth_cmp1_init()
558 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth_cmp1_init()
565 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0), in vsc85xx_eth_cmp1_init()
577 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER, in vsc85xx_ip_cmp1_init()
580 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER, in vsc85xx_ip_cmp1_init()
582 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER, in vsc85xx_ip_cmp1_init()
584 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0); in vsc85xx_ip_cmp1_init()
589 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip_cmp1_init()
592 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0); in vsc85xx_ip_cmp1_init()
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
596 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0), in vsc85xx_ip_cmp1_init()
598 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
600 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0), in vsc85xx_ip_cmp1_init()
602 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0); in vsc85xx_ip_cmp1_init()
605 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0); in vsc85xx_ip_cmp1_init()
631 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ, in vsc85xx_adjfine()
637 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in vsc85xx_adjfine()
655 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_gettime()
704 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB, in __vsc85xx_settime()
706 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB, in __vsc85xx_settime()
708 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS, in __vsc85xx_settime()
713 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
722 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc85xx_settime()
773 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val); in vsc85xx_adjtime()
788 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val); in vsc85xx_eth1_next_comp()
792 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_next_comp()
801 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, in vsc85xx_ip1_next_comp()
814 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
826 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow), in vsc85xx_ts_ptp_action_flow()
841 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_ts_ptp_action_flow()
874 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), in vsc85xx_ptp_conf()
893 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
895 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
900 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
902 vsc85xx_ts_write_csr(phydev, blk, in vsc85xx_eth1_conf()
910 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val); in vsc85xx_eth1_conf()
920 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE, in vsc85xx_ip1_conf()
928 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1, in vsc85xx_ip1_conf()
932 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2, in vsc85xx_ip1_conf()
947 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM, in vsc85xx_ip1_conf()
955 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val); in vsc85xx_ip1_conf()
974 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
1018 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in vsc85xx_ts_engine_init()
1040 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1044 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in vsc85xx_ts_reset_fifo()
1098 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1103 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1113 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in vsc85xx_hwtstamp()
1124 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in vsc85xx_hwtstamp()
1129 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in vsc85xx_hwtstamp()
1294 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR, in __vsc8584_init_ptp()
1299 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR, in __vsc8584_init_ptp()
1306 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val); in __vsc8584_init_ptp()
1311 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val); in __vsc8584_init_ptp()
1318 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val); in __vsc8584_init_ptp()
1320 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ, in __vsc8584_init_ptp()
1323 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO, in __vsc8584_init_ptp()
1328 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO, in __vsc8584_init_ptp()
1344 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1350 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1361 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1367 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1373 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS, in __vsc8584_init_ptp()
1380 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI, in __vsc8584_init_ptp()
1386 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1391 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1398 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1404 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL, in __vsc8584_init_ptp()
1413 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL, in __vsc8584_init_ptp()
1418 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val); in __vsc8584_init_ptp()
1423 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE, in __vsc8584_init_ptp()
1434 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL, in __vsc8584_init_ptp()
1442 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1450 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val); in __vsc8584_init_ptp()
1467 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE, in __vsc8584_init_ptp()
1502 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK, in vsc8584_config_ts_intr()
1530 vsc85xx_ts_write_csr(phydev, PROCESSOR, in vsc8584_handle_ts_interrupt()