718 int phy_base_read(struct phy_device *phydev, u32 regnum)  in phy_base_read()  function
763 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_read()
771 	val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);  in vsc85xx_csr_read()
774 	val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);  in vsc85xx_csr_read()
822 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);  in vsc85xx_csr_write()
856 		reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);  in vsc8584_cmd()
918 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
925 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
931 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8584_micro_assert_reset()
939 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_micro_assert_reset()
966 	*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);  in vsc8584_get_fw_crc()
1021 	reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));  in vsc8574_is_serdes_init()
1027 	reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));  in vsc8574_is_serdes_init()
1033 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8574_is_serdes_init()
1039 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);  in vsc8574_is_serdes_init()
1130 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1150 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1170 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8574_config_pre_init()
1177 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8574_config_pre_init()
1389 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1395 	reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);  in vsc8584_config_pre_init()
1412 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1420 	reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);  in vsc8584_config_pre_init()
1441 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8584_config_pre_init()
1448 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8584_config_pre_init()
1502 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8584_config_pre_init()
1584 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8584_config_host_serdes()
1649 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8574_config_host_serdes()
1920 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);  in vsc8514_config_host_serdes()
1954 	val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8514_config_host_serdes()
2006 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
2012 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
2023 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);  in vsc8514_config_pre_init()
2029 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);  in vsc8514_config_pre_init()
2054 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);  in vsc8514_config_pre_init()