phy/mscc/mscc_mac.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
77 #define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA				BIT(0)
78 #define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA				BIT(4)
79 #define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST				BIT(8)
80 #define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST				BIT(12)
81 #define MSCC_MAC_CFG_ENA_CFG_RX_ENA				BIT(16)
82 #define MSCC_MAC_CFG_ENA_CFG_TX_ENA				BIT(20)
84 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x)	((x) << 20)
85 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M	GENMASK(29, 20)
86 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE			BIT(16)
87 #define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES		BIT(14)
90 #define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG			BIT(6)
91 #define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA		BIT(4)
92 #define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK			BIT(2)
93 #define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS		BIT(1)
94 #define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC			BIT(0)
96 #define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK			BIT(16)
103 #define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA				BIT(4)
105 #define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA		BIT(24)
106 #define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA		BIT(20)
107 #define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA			BIT(16)
108 #define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS		BIT(12)
109 #define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA			BIT(8)
110 #define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA			BIT(4)
111 #define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA			BIT(0)
113 #define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX				BIT(8)
114 #define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX				BIT(4)
115 #define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA			BIT(3)
116 #define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT		BIT(2)
117 #define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS			BIT(1)
118 #define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA			BIT(0)
120 #define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA			BIT(4)
121 #define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA			BIT(0)
123 #define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA			BIT(0)
124 #define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA			BIT(4)
125 #define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA		BIT(8)
126 #define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA		BIT(12)
127 #define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA			BIT(16)
128 #define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA			BIT(20)
129 #define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA			BIT(24)
130 #define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING		BIT(25)
131 #define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING		BIT(26)
132 #define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE		BIT(27)
138 #define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW	BIT(12)
139 #define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA	BIT(8)
140 #define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE	BIT(4)
141 #define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME	BIT(2)
145 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA	BIT(16)
146 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE		BIT(20)
147 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA	BIT(12)
148 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA	BIT(8)
149 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA	BIT(4)
150 #define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE		BIT(0)
152 #define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE			BIT(0)
153 #define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN		BIT(4)