Lines Matching refs:PHYACC_ATTR_BANK_SMI
52 #define PHYACC_ATTR_BANK_SMI 0 macro
148 if (bank == PHYACC_ATTR_BANK_SMI) { in access_ereg()
255 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) { in lan87xx_phy_init_cmd()
279 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
406 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
409 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
412 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
415 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
421 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
427 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, in lan87xx_phy_init()
623 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, in lan87xx_cable_test_start()
629 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI, in lan87xx_cable_test_start()
640 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, in lan87xx_cable_test_start()
646 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI, in lan87xx_cable_test_start()