net/phy/mediatek-ge.c

6 #define MTK_EXT_PAGE_ACCESS		0x1f
7 #define MTK_PHY_PAGE_STANDARD		0x0000
8 #define MTK_PHY_PAGE_EXTENDED		0x0001
9 #define MTK_PHY_PAGE_EXTENDED_2		0x0002
10 #define MTK_PHY_PAGE_EXTENDED_3		0x0003
11 #define MTK_PHY_PAGE_EXTENDED_2A30	0x2a30
12 #define MTK_PHY_PAGE_EXTENDED_52B5	0x52b5
27 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);  in mtk_gephy_config_init()
30 	phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));  in mtk_gephy_config_init()
34 	__phy_write(phydev, 0x10, 0xafae);  in mtk_gephy_config_init()
35 	__phy_write(phydev, 0x12, 0x2f);  in mtk_gephy_config_init()
36 	__phy_write(phydev, 0x10, 0x8fae);  in mtk_gephy_config_init()
37 	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);  in mtk_gephy_config_init()
40 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);  in mtk_gephy_config_init()
43 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);  in mtk_gephy_config_init()
51 	phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);  in mt7530_phy_config_init()
53 	return 0;  in mt7530_phy_config_init()
61 	phy_set_bits(phydev, 0x17, BIT(4));  in mt7531_phy_config_init()
62 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);  in mt7531_phy_config_init()
65 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);  in mt7531_phy_config_init()
66 	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);  in mt7531_phy_config_init()
68 	return 0;  in mt7531_phy_config_init()
73 		PHY_ID_MATCH_EXACT(0x03a29412),
87 		PHY_ID_MATCH_EXACT(0x03a29441),
105 	{ PHY_ID_MATCH_EXACT(0x03a29441) },
106 	{ PHY_ID_MATCH_EXACT(0x03a29412) },