Lines Matching +full:5 +full:gbase +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
171 return phydev->drv->driver_data; in to_mv3310_chip()
209 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
213 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
218 return -EOPNOTSUPP; in mv3310_hwmon_read()
262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
278 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
282 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); in mv3310_hwmon_probe()
283 if (!priv->hwmon_name) in mv3310_hwmon_probe()
284 return -ENODEV; in mv3310_hwmon_probe()
286 for (i = j = 0; priv->hwmon_name[i]; i++) { in mv3310_hwmon_probe()
287 if (isalnum(priv->hwmon_name[i])) { in mv3310_hwmon_probe()
289 priv->hwmon_name[j] = priv->hwmon_name[i]; in mv3310_hwmon_probe()
293 priv->hwmon_name[j] = '\0'; in mv3310_hwmon_probe()
299 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, in mv3310_hwmon_probe()
300 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
303 return PTR_ERR_OR_ZERO(priv->hwmon_dev); in mv3310_hwmon_probe()
325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
338 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
339 priv->firmware_ver < 0x00030000) in mv3310_power_up()
363 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_get_downshift()
366 if (!priv->has_downshift) in mv3310_get_downshift()
367 return -EOPNOTSUPP; in mv3310_get_downshift()
384 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_set_downshift()
388 if (!priv->has_downshift) in mv3310_set_downshift()
389 return -EOPNOTSUPP; in mv3310_set_downshift()
397 * "ethtool --set-phy-tunable ethN downshift on". The intention is in mv3310_set_downshift()
406 return -E2BIG; in mv3310_set_downshift()
408 ds -= 1; in mv3310_set_downshift()
468 return -EINVAL; in mv3310_set_edpd()
486 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); in mv3310_sfp_insert()
487 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
490 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
491 return -EINVAL; in mv3310_sfp_insert()
509 if (!phydev->is_c45 || in mv3310_probe()
510 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
511 return -ENODEV; in mv3310_probe()
518 dev_warn(&phydev->mdio.dev, in mv3310_probe()
519 "PHY failed to boot firmware, status=%04x\n", ret); in mv3310_probe()
520 return -ENODEV; in mv3310_probe()
523 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
525 return -ENOMEM; in mv3310_probe()
527 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
533 priv->firmware_ver = ret << 16; in mv3310_probe()
539 priv->firmware_ver |= ret; in mv3310_probe()
542 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, in mv3310_probe()
543 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); in mv3310_probe()
545 if (chip->has_downshift) in mv3310_probe()
546 priv->has_downshift = chip->has_downshift(phydev); in mv3310_probe()
557 chip->init_supported_interfaces(priv->supported_interfaces); in mv3310_probe()
585 * support 2.5GBASET and 5GBASET. For these models, we can still read their
586 * 2.5G/5G extended abilities register (1.21). We detect these models based on
592 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
596 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
651 return -1; in mv2110_select_mactype()
702 return -1; in mv3310_select_mactype()
707 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv2110_init_interface()
709 priv->rate_match = false; in mv2110_init_interface()
712 priv->rate_match = true; in mv2110_init_interface()
715 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv2110_init_interface()
717 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv2110_init_interface()
720 priv->const_interface = PHY_INTERFACE_MODE_NA; in mv2110_init_interface()
722 return -EINVAL; in mv2110_init_interface()
729 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_init_interface()
731 priv->rate_match = false; in mv3310_init_interface()
736 priv->rate_match = true; in mv3310_init_interface()
739 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv3310_init_interface()
743 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv3310_init_interface()
746 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3310_init_interface()
749 priv->const_interface = PHY_INTERFACE_MODE_XAUI; in mv3310_init_interface()
751 return -EINVAL; in mv3310_init_interface()
758 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3340_init_interface()
761 priv->rate_match = false; in mv3340_init_interface()
764 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3340_init_interface()
773 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
778 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
779 return -ENODEV; in mv3310_config_init()
781 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
791 if (!phy_interface_empty(phydev->host_interfaces)) { in mv3310_config_init()
792 mactype = chip->select_mactype(phydev->host_interfaces); in mv3310_config_init()
796 err = chip->set_mactype(phydev, mactype); in mv3310_config_init()
802 mactype = chip->get_mactype(phydev); in mv3310_config_init()
806 err = chip->init_interface(phydev, mactype); in mv3310_config_init()
812 /* Enable EDPD mode - saving 600mW */ in mv3310_config_init()
819 if (err && err != -EOPNOTSUPP) in mv3310_config_init()
840 phydev->supported, in mv3310_get_features()
844 phydev->supported, in mv3310_get_features()
856 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
867 return -EINVAL; in mv3310_config_mdix()
888 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
900 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
927 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
929 if (!phydev->link) in mv3310_update_interface()
938 if (priv->rate_match || in mv3310_update_interface()
939 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { in mv3310_update_interface()
940 phydev->interface = priv->const_interface; in mv3310_update_interface()
945 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
947 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
950 switch (phydev->speed) { in mv3310_update_interface()
952 phydev->interface = priv->const_interface; in mv3310_update_interface()
955 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
958 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
963 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
970 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
973 phydev->link = 1; in mv3310_read_status_10gbaser()
974 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
975 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
976 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
999 phydev->link = 0; in mv3310_read_status_copper()
1010 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
1014 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
1018 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
1022 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
1026 phydev->speed = SPEED_100; in mv3310_read_status_copper()
1030 phydev->speed = SPEED_10; in mv3310_read_status_copper()
1034 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
1036 phydev->port = PORT_TP; in mv3310_read_status_copper()
1037 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
1050 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
1063 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
1064 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
1065 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
1066 phydev->link = 0; in mv3310_read_status()
1067 phydev->pause = 0; in mv3310_read_status()
1068 phydev->asym_pause = 0; in mv3310_read_status()
1069 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
1082 if (phydev->link) in mv3310_read_status()
1091 switch (tuna->id) { in mv3310_get_tunable()
1097 return -EOPNOTSUPP; in mv3310_get_tunable()
1104 switch (tuna->id) { in mv3310_set_tunable()
1110 return -EOPNOTSUPP; in mv3310_set_tunable()
1116 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_has_downshift()
1119 return priv->firmware_ver >= MV_VERSION(0,3,5,0); in mv3310_has_downshift()
1226 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1235 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1246 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1272 wol->supported = WAKE_MAGIC; in mv3110_get_wol()
1273 wol->wolopts = 0; in mv3110_get_wol()
1280 wol->wolopts |= WAKE_MAGIC; in mv3110_get_wol()
1288 if (wol->wolopts & WAKE_MAGIC) { in mv3110_set_wol()
1299 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1300 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1306 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1307 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1313 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1314 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1335 /* Reset the clear WOL status bit as it does not self-clear */ in mv3110_set_wol()
1430 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");