Lines Matching +full:0 +full:x431
20 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22 #define MII_BCM7XXX_100TX_DISC 0x14
23 #define MII_BCM7XXX_AUX_MODE 0x1d
25 #define MII_BCM7XXX_TEST 0x1f
27 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
28 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
29 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30 #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31 #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
32 #define MII_BCM7XXX_SHD_3_EEE_CAP 0x2
33 #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
34 #define MII_BCM7XXX_SHD_3_EEE_LP 0x4
35 #define MII_BCM7XXX_SHD_3_EEE_WK_ERR 0x5
36 #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
37 #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
38 #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
39 #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
41 #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
42 #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
43 #define MII_BCM7XXX_SHD_3_TL4 0x23
53 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
56 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
58 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
59 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
62 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
65 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
68 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
71 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
74 * offset for HT=0 code in bcm7xxx_28nm_d0_afe_config_init()
76 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
81 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ in bcm7xxx_28nm_d0_afe_config_init()
82 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
87 return 0; in bcm7xxx_28nm_d0_afe_config_init()
93 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
96 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
99 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
102 * offset for HT=0 code in bcm7xxx_28nm_e0_plus_afe_config_init()
104 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
109 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ in bcm7xxx_28nm_e0_plus_afe_config_init()
110 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
115 return 0; in bcm7xxx_28nm_e0_plus_afe_config_init()
121 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
124 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
127 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
129 /* Change rx_on_tune 8 to 0xf */ in bcm7xxx_28nm_a0_patch_afe_config_init()
130 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
133 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
136 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
140 return 0; in bcm7xxx_28nm_a0_patch_afe_config_init()
148 int ret = 0; in bcm7xxx_28nm_config_init()
153 if (rev == 0) in bcm7xxx_28nm_config_init()
156 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", in bcm7xxx_28nm_config_init()
161 * the MDIO management controller and make us return 0xffff for such in bcm7xxx_28nm_config_init()
167 case 0xa0: in bcm7xxx_28nm_config_init()
168 case 0xb0: in bcm7xxx_28nm_config_init()
171 case 0xd0: in bcm7xxx_28nm_config_init()
174 case 0xe0: in bcm7xxx_28nm_config_init()
175 case 0xf0: in bcm7xxx_28nm_config_init()
177 case 0x10: in bcm7xxx_28nm_config_init()
180 case 0x01: in bcm7xxx_28nm_config_init()
229 if (v < 0) in __phy_set_clr_bits()
236 if (ret < 0) in __phy_set_clr_bits()
260 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_01_afe_config_init()
261 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
264 /* Set current trim values INT_trim = -1, Ext_trim =0 */ in bcm7xxx_28nm_ephy_01_afe_config_init()
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
266 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
272 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
275 MII_BCM7XXX_TL4_RST_MSK, 0); in bcm7xxx_28nm_ephy_01_afe_config_init()
276 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
282 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
285 0, MII_BCM7XXX_TL4_RST_MSK); in bcm7xxx_28nm_ephy_01_afe_config_init()
286 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
291 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
293 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
296 return 0; in bcm7xxx_28nm_ephy_01_afe_config_init()
306 MII_BRCM_FET_BT_SRE, 0); in bcm7xxx_28nm_ephy_apd_enable()
307 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
312 MII_BRCM_FET_SHDW_AS2_APDE, 0); in bcm7xxx_28nm_ephy_apd_enable()
313 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
317 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
319 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
322 return 0; in bcm7xxx_28nm_ephy_apd_enable()
331 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_eee_enable()
332 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
338 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
342 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
348 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
352 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
357 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
361 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
367 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
371 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
376 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
378 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
385 return 0; in bcm7xxx_28nm_ephy_eee_enable()
391 int ret = 0; in bcm7xxx_28nm_ephy_config_init()
393 pr_info_once("%s: %s PHY revision: 0x%02x\n", in bcm7xxx_28nm_ephy_config_init()
398 * to pass the MDIO management controller and make us return 0xffff for in bcm7xxx_28nm_ephy_config_init()
404 if (rev == 0x01) { in bcm7xxx_28nm_ephy_config_init()
427 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006); in bcm7xxx_16nm_ephy_afe_config()
429 bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
432 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
433 bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a); in bcm7xxx_16nm_ephy_afe_config()
436 bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1); in bcm7xxx_16nm_ephy_afe_config()
438 bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000); in bcm7xxx_16nm_ephy_afe_config()
441 bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68); in bcm7xxx_16nm_ephy_afe_config()
442 bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
447 bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036); in bcm7xxx_16nm_ephy_afe_config()
450 bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
452 bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002); in bcm7xxx_16nm_ephy_afe_config()
454 bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0); in bcm7xxx_16nm_ephy_afe_config()
456 bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
459 bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010); in bcm7xxx_16nm_ephy_afe_config()
462 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038); in bcm7xxx_16nm_ephy_afe_config()
463 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b); in bcm7xxx_16nm_ephy_afe_config()
465 bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f); in bcm7xxx_16nm_ephy_afe_config()
469 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82); in bcm7xxx_16nm_ephy_afe_config()
471 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82); in bcm7xxx_16nm_ephy_afe_config()
474 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82); in bcm7xxx_16nm_ephy_afe_config()
477 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86); in bcm7xxx_16nm_ephy_afe_config()
480 bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86); in bcm7xxx_16nm_ephy_afe_config()
484 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea); in bcm7xxx_16nm_ephy_afe_config()
486 bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0); in bcm7xxx_16nm_ephy_afe_config()
489 tmp = bcm_phy_read_exp_sel(phydev, 0x00a9); in bcm7xxx_16nm_ephy_afe_config()
490 /* CORE_EXPA9[6:1] is rcalcode[5:0] */ in bcm7xxx_16nm_ephy_afe_config()
491 rcalcode = (tmp & 0x7e) / 2; in bcm7xxx_16nm_ephy_afe_config()
497 if (rcalnewcodelp > 0x3f) in bcm7xxx_16nm_ephy_afe_config()
498 rcalnewcodelp = 0x3f; in bcm7xxx_16nm_ephy_afe_config()
499 if (rcalnewcode11 > 0x3f) in bcm7xxx_16nm_ephy_afe_config()
500 rcalnewcode11 = 0x3f; in bcm7xxx_16nm_ephy_afe_config()
501 /* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */ in bcm7xxx_16nm_ephy_afe_config()
502 tmp = 0x00f8 + rcalnewcodelp * 256; in bcm7xxx_16nm_ephy_afe_config()
504 bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp); in bcm7xxx_16nm_ephy_afe_config()
506 bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4); in bcm7xxx_16nm_ephy_afe_config()
510 bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002); in bcm7xxx_16nm_ephy_afe_config()
512 bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882); in bcm7xxx_16nm_ephy_afe_config()
516 bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201); in bcm7xxx_16nm_ephy_afe_config()
518 bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00); in bcm7xxx_16nm_ephy_afe_config()
523 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020); in bcm7xxx_16nm_ephy_afe_config()
526 bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
527 bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
530 bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800); in bcm7xxx_16nm_ephy_afe_config()
533 /* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr in bcm7xxx_16nm_ephy_afe_config()
536 bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
539 rcalnewcode11d2 = (rcalnewcode11 & 0xfffe) / 2; in bcm7xxx_16nm_ephy_afe_config()
540 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001); in bcm7xxx_16nm_ephy_afe_config()
542 tmp &= ~0xfe0; in bcm7xxx_16nm_ephy_afe_config()
544 tmp |= 0x0020 | (rcalnewcode11d2 * 64); in bcm7xxx_16nm_ephy_afe_config()
545 bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp); in bcm7xxx_16nm_ephy_afe_config()
546 bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp); in bcm7xxx_16nm_ephy_afe_config()
548 tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000); in bcm7xxx_16nm_ephy_afe_config()
551 tmp &= ~0x3000; in bcm7xxx_16nm_ephy_afe_config()
552 tmp |= 0x3000; in bcm7xxx_16nm_ephy_afe_config()
553 bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp); in bcm7xxx_16nm_ephy_afe_config()
555 return 0; in bcm7xxx_16nm_ephy_afe_config()
571 if (ret < 0) in bcm7xxx_16nm_ephy_config_init()
583 if (ret < 0) in bcm7xxx_16nm_ephy_config_init()
601 #define MII_BCM7XXX_REG_INVALID 0xff
640 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_read_mmd()
641 if (ret < 0) in bcm7xxx_28nm_ephy_read_mmd()
646 if (ret < 0) in bcm7xxx_28nm_ephy_read_mmd()
653 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
670 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_write_mmd()
671 if (ret < 0) in bcm7xxx_28nm_ephy_write_mmd()
676 if (ret < 0) in bcm7xxx_28nm_ephy_write_mmd()
684 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
711 if (ret < 0) in bcm7xxx_config_init()
715 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
719 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
721 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
724 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
725 if (ret < 0) in bcm7xxx_config_init()
728 return 0; in bcm7xxx_config_init()
741 { MII_BCM7XXX_TEST, 0x008b }, in bcm7xxx_suspend()
742 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 }, in bcm7xxx_suspend()
743 { MII_BCM7XXX_100TX_DISC, 0x7000 }, in bcm7xxx_suspend()
744 { MII_BCM7XXX_TEST, 0x000f }, in bcm7xxx_suspend()
745 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 }, in bcm7xxx_suspend()
746 { MII_BCM7XXX_TEST, 0x000b }, in bcm7xxx_suspend()
750 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) { in bcm7xxx_suspend()
758 return 0; in bcm7xxx_suspend()
814 int ret = 0; in bcm7xxx_28nm_probe()
834 * the MDIO management controller and make us return 0xffff for such in bcm7xxx_28nm_probe()
846 .phy_id_mask = 0xfffffff0, \
863 .phy_id_mask = 0xfffffff0, \
880 .phy_id_mask = 0xfffffff0, \
893 .phy_id_mask = 0xfffffff0, \
933 { PHY_ID_BCM72113, 0xfffffff0 },
934 { PHY_ID_BCM72116, 0xfffffff0, },
935 { PHY_ID_BCM72165, 0xfffffff0, },
936 { PHY_ID_BCM7250, 0xfffffff0, },
937 { PHY_ID_BCM7255, 0xfffffff0, },
938 { PHY_ID_BCM7260, 0xfffffff0, },
939 { PHY_ID_BCM7268, 0xfffffff0, },
940 { PHY_ID_BCM7271, 0xfffffff0, },
941 { PHY_ID_BCM7278, 0xfffffff0, },
942 { PHY_ID_BCM7364, 0xfffffff0, },
943 { PHY_ID_BCM7366, 0xfffffff0, },
944 { PHY_ID_BCM7346, 0xfffffff0, },
945 { PHY_ID_BCM7362, 0xfffffff0, },
946 { PHY_ID_BCM7425, 0xfffffff0, },
947 { PHY_ID_BCM7429, 0xfffffff0, },
948 { PHY_ID_BCM74371, 0xfffffff0, },
949 { PHY_ID_BCM7439, 0xfffffff0, },
950 { PHY_ID_BCM7435, 0xfffffff0, },
951 { PHY_ID_BCM7445, 0xfffffff0, },
952 { PHY_ID_BCM7712, 0xfffffff0, },