72 	int ret;  in adin_read_status()  local
74 	ret = genphy_c45_read_status(phydev);  in adin_read_status()
75 	if (ret)  in adin_read_status()
76 		return ret;  in adin_read_status()
78 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);  in adin_read_status()
79 	if (ret < 0)  in adin_read_status()
80 		return ret;  in adin_read_status()
82 	if (ret & ADIN_IS_CFG_SLV)  in adin_read_status()
85 	if (ret & ADIN_IS_CFG_MST)  in adin_read_status()
94 	int ret;  in adin_config_aneg()  local
97 		ret = genphy_c45_pma_setup_forced(phydev);  in adin_config_aneg()
98 		if (ret < 0)  in adin_config_aneg()
99 			return ret;  in adin_config_aneg()
102 			ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,  in adin_config_aneg()
105 			ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,  in adin_config_aneg()
107 		if (ret < 0)  in adin_config_aneg()
108 			return ret;  in adin_config_aneg()
114 	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);  in adin_config_aneg()
115 	if (ret < 0)  in adin_config_aneg()
116 		return ret;  in adin_config_aneg()
120 		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,  in adin_config_aneg()
123 		if (ret < 0)  in adin_config_aneg()
124 			return ret;  in adin_config_aneg()
129 		ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,  in adin_config_aneg()
132 		if (ret < 0)  in adin_config_aneg()
133 			return ret;  in adin_config_aneg()
141 	int ret;  in adin_set_powerdown_mode()  local
145 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,  in adin_set_powerdown_mode()
147 	if (ret < 0)  in adin_set_powerdown_mode()
148 		return ret;  in adin_set_powerdown_mode()
150 	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,  in adin_set_powerdown_mode()
151 					 (ret & ADIN_CRSM_SFT_PD_RDY) == val,  in adin_set_powerdown_mode()
178 	int ret;  in adin_soft_reset()  local
180 	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);  in adin_soft_reset()
181 	if (ret < 0)  in adin_soft_reset()
182 		return ret;  in adin_soft_reset()
184 	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,  in adin_soft_reset()
185 					 (ret & ADIN_CRSM_SYS_RDY),  in adin_soft_reset()
193 	int ret;  in adin_get_features()  local
196 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);  in adin_get_features()
197 	if (ret < 0)  in adin_get_features()
198 		return ret;  in adin_get_features()
201 	priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);  in adin_get_features()
208 		ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);  in adin_get_features()
209 		if (ret < 0)  in adin_get_features()
210 			return ret;  in adin_get_features()
228 	int ret;  in adin_get_sqi()  local
230 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);  in adin_get_sqi()
231 	if (ret < 0)  in adin_get_sqi()
232 		return ret;  in adin_get_sqi()
233 	else if (!(ret & MDIO_STAT1_LSTATUS))  in adin_get_sqi()
236 	ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);  in adin_get_sqi()
237 	if (ret < 0)  in adin_get_sqi()
238 		return ret;  in adin_get_sqi()
240 	mse_val = 0xFFFF & ret;  in adin_get_sqi()