Lines Matching refs:ETH_PLL_CTL0

19 #define ETH_PLL_CTL0		0x44  macro
75 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_recalc_rate()
85 	u32 val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
89 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
93 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
100 	return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,  in g12a_ephy_pll_enable()
109 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_disable()
112 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_disable()
120 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_is_enabled()
130 	writel(0x29c0040a, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_init()
261 	mux->reg = priv->regs + ETH_PLL_CTL0;  in g12a_ephy_glue_clk_register()