402 	struct regmap *regmap_iar;  member
576 		regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr);  in mcr20a_set_hw_addr_filt()
577 		regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8);  in mcr20a_set_hw_addr_filt()
583 		regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan);  in mcr20a_set_hw_addr_filt()
584 		regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8);  in mcr20a_set_hw_addr_filt()
592 			regmap_write(lp->regmap_iar,  in mcr20a_set_hw_addr_filt()
680 			ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL,  in mcr20a_set_cca_mode()
684 			ret = regmap_update_bits(lp->regmap_iar,  in mcr20a_set_cca_mode()
706 			return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i);  in mcr20a_set_cca_ed_level()
733 		ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_set_promiscuous_mode()
743 		ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_set_promiscuous_mode()
1089 	ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02);  in mcr20a_phy_init()
1139 	ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER,  in mcr20a_phy_init()
1157 	ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites,  in mcr20a_phy_init()
1176 	ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg);  in mcr20a_phy_init()
1186 	ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg);  in mcr20a_phy_init()
1191 	ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B);  in mcr20a_phy_init()
1196 	ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05);  in mcr20a_phy_init()
1284 	lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap);  in mcr20a_probe()
1285 	if (IS_ERR(lp->regmap_iar)) {  in mcr20a_probe()
1286 		ret = PTR_ERR(lp->regmap_iar);  in mcr20a_probe()