net/hamradio/z8530.h

1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
28 #define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
29 #define	RES_Tx_P	0x28	/* Reset TxINT Pending */
30 #define	ERR_RES		0x30	/* Error Reset */
31 #define	RES_H_IUS	0x38	/* Reset highest IUS */
33 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
34 #define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
35 #define	RES_EOM_L	0xC0	/* Reset EOM latch */
58 #define	ADD_SM		0x4	/* Address Search Mode (SDLC) */
60 #define	ENT_HM		0x10	/* Enter Hunt Mode */
79 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
80 #define	EXTSYNC		0x30	/* External Sync Mode */
82 #define	X1CLK		0x0	/* x1 clock mode */
83 #define	X16CLK		0x40	/* x16 clock mode */
84 #define	X32CLK		0x80	/* x32 clock mode */
85 #define	X64CLK		0xC0	/* x64 clock mode */
91 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
112 #define	NORESET	0	/* No reset on write to R9 */
113 #define	CHRB	0x40	/* Reset channel B */
114 #define	CHRA	0x80	/* Reset channel A */
115 #define	FHWRES	0xc0	/* Force hardware reset */
119 #define	LOOPMODE 2	/* SDLC Loop mode */
123 #define	NRZ	0	/* NRZ mode */
124 #define	NRZI	0x20	/* NRZI mode */
129 /* Write Register 11 (Clock Mode control) */
155 #define	SEARCH	0x20	/* Enter search mode */
156 #define	RMC	0x40	/* Reset missing clock */
160 #define	SFMM	0xc0	/* Set FM mode */
161 #define	SNRZI	0xe0	/* Set NRZI mode */
199 /* Read Register 2 (channel b only) - Interrupt vector */
227 #define AUTOEOM 0x02		/* Auto EOM Latch Reset */
229 #define TXDNRZI 0x08		/* TxD Pulled High in SDLC NRZI mode */
231 #define FASTDTR 0x10		/* Fast DTR/REQ Mode */