Lines Matching +full:full +full:- +full:frame
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 * FORMAC frame status (rx_msext)
47 #define FS_MSRABT (1<<14) /* frame was aborted during reception*/
48 #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
54 #define FS_SFRMTY2 (1<<6) /* frame-class bit */
55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
56 #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
58 #define FS_ERFBB0 (1<<0) /* - " - */
61 * status frame type
71 * bits in rx_descr.i (receive frame status word)
80 #define RX_FS_MAC ((long)FS_SFRMTY2<<16)/* MAC frame */
81 #define RX_FS_SMT ((long)0<<16) /* SMT frame */
82 #define RX_FS_IMPL ((long)FS_SFRMTY1<<16)/* implementer frame */
83 #define RX_FS_LLC ((long)FS_SFRMTY0<<16)/* LLC frame */
86 * receive frame descriptor
91 unsigned int rx_length :16 ; /* frame length lower/upper byte */
92 unsigned int rx_erfbb :2 ; /* received frame byte boundary */
94 unsigned int rx_sfrmty :3 ; /* frame type bits */
95 unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
96 unsigned int rx_sfrmerr:1 ; /* received frame not valid */
97 unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */
98 unsigned int rx_seac1 :1 ; /* address-match A-indicator */
99 unsigned int rx_seac2 :1 ; /* frame-error E-indicator */
109 unsigned int rx_seac2 :1 ; /* frame-error E-indicator */
110 unsigned int rx_seac1 :1 ; /* address-match A-indicator */
111 unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */
112 unsigned int rx_sfrmerr:1 ; /* received frame not valid */
113 unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
114 unsigned int rx_sfrmty :3 ; /* frame type bits */
115 unsigned int rx_erfbb :2 ; /* received frame byte boundary */
117 unsigned int rx_length :16 ; /* frame length lower/upper byte */
123 /* defines for Receive Frame Descriptor access */
124 #define RD_S_ERFBB 0x00030000L /* received frame byte boundary */
126 #define RD_S_SFRMTY 0x00700000L /* frame type bits */
127 #define RD_S_SADRRG 0x00800000L /* DA == MA or broad-/multicast */
128 #define RD_S_SFRMERR 0x01000000L /* received frame not valid */
129 #define RD_S_SEAC 0x0e000000L /* frame status indicators */
130 #define RD_S_SEAC0 0x02000000L /* frame-copied case-indicator */
131 #define RD_S_SEAC1 0x04000000L /* address-match A-indicator */
132 #define RD_S_SEAC2 0x08000000L /* frame-error E-indicator */
156 * transmit frame descriptor
161 unsigned int tx_length:16 ; /* frame length lower/upper byte */
164 unsigned int tx_nfcs :1 ; /* no frame check sequence */
168 unsigned int tx_more :1 ; /* more frame in chain */
170 unsigned int tx_more :1 ; /* more frame in chain */
174 unsigned int tx_nfcs :1 ; /* no frame check sequence */
177 unsigned int tx_length:16 ; /* frame length lower/upper byte */
184 #define TD_C_MORE 0x80000000L /* more frame in chain */
188 #define TD_C_NFCS 0x02000000L /* no frame check sequence */
193 #define TD_C_LNCN 0x0000ffffL /* frame length lower/upper byte */
239 #define FM_ST1U 0x00 /* read upper 16-bit of status reg 1 */
240 #define FM_ST1L 0x01 /* read lower 16-bit of status reg 1 */
241 #define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */
242 #define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */
243 #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
244 #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
245 #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
246 #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
247 #define FM_SAID 0x08 /* r/w short addr.-individual */
248 #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
249 #define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/
250 #define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */
251 #define FM_SAGP 0x0c /* r/w short address-group */
252 #define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */
253 #define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */
254 #define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */
255 #define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */
256 #define FM_STMCHN 0x11 /* read state-machine reg */
257 #define FM_MIR1 0x12 /* read upper 16-bit of MAC Info Reg */
258 #define FM_MIR0 0x13 /* read lower 16-bit of MAC Info Reg */
259 #define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */
260 #define FM_TVX 0x15 /* write 8-bit TVX reg with NP7-0
261 read TVX on NP7-0, timer on NP15-8*/
262 #define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */
263 #define FM_THT 0x17 /* r/w upper 16-bit of THT timer */
264 #define FM_TNEG 0x18 /* read upper 16-bit of TNEG (TTRT) */
265 #define FM_TMRS 0x19 /* read lower 5-bit of TNEG,TRT,THT */
267 x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
268 #define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
269 #define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
270 #define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */
271 #define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */
272 #define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */
273 #define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */
274 #define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */
275 #define FM_FRMTHR 0x21 /* r/w the frame threshold register */
285 #define FM_SACL 0x28 /* r/w start addr of claim frame */
286 #define FM_SABC 0x29 /* r/w start addr of beacon frame */
291 #define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
301 #define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
302 #define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
303 #define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
304 #define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
311 #define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */
312 #define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */
316 #define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */
317 #define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */
318 #define FM_ECNTR 0x43 /* r/w the 16-bit error counter */
321 #define FM_FSCNTR 0x44 /* r/? Frame Strip Counter */
322 #define FM_FRSELREG 0x45 /* r/w Frame Selection Register */
326 #define FM_ST3U 0x61 /* read upper 16-bit of status reg 3 */
327 #define FM_ST3L 0x62 /* read lower 16-bit of status reg 3 */
328 #define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */
329 #define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */
338 /* Bit 15-8: RECV2 unlock threshold */
339 /* Bit 7-0: RECV1 unlock threshold */
340 /* 0x6f-0x73 Hidden */
342 /* 0x80-0x9a PLCS registers of built-in PLCS (Supernet 3 only) */
366 #define FM_XMTINH_HOLD 0x0002 /* transmit-inhibit/hold bit */
369 #define FM_FULL_HALF 0x0004 /* full-duplex/half-duplex bit */
370 #define FM_LOCKTX 0x0008 /* lock-transmit-asynchr.-queues bit */
371 #define FM_EXGPA0 0x0010 /* extended-group-addressing bit 0 */
372 #define FM_EXGPA1 0x0020 /* extended-group-addressing bit 1 */
373 #define FM_DISCRY 0x0040 /* disable-carry bit */
380 #define FM_MRNNSAFNMA (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */
381 #define FM_MRNNSAF (3<<8) /* rec. non-NSA frames DA = MA */
384 #define FM_MLIMPROM (6<<8) /* limited-promiscuous mode */
387 #define FM_SELSA 0x0800 /* select-short-address bit */
392 #define FM_MONLINESP (2<<12) /* on-line special */
393 #define FM_MONLINE (3<<12) /* on-line (FDDI operational mode) */
399 #define FM_SNGLFRM 0x8000 /* single-frame-receive mode */
407 #define FM_AFULL 0x000f /* 4-bit value (empty loc.in txqueue)*/
408 #define FM_RCVERR 0x0010 /* rec.-errored-frames bit */
409 #define FM_SYMCTL 0x0020 /* sysmbol-control bit */
411 #define FM_SYNPRQ 0x0040 /* synchron.-NP-DMA-request bit */
412 #define FM_ENNPRQ 0x0080 /* enable-NP-DMA-request bit */
413 #define FM_ENHSRQ 0x0100 /* enable-host-request bit */
414 #define FM_RXFBB01 0x0600 /* rec. frame byte boundary bit0 & 1 */
417 #define FM_CHKPAR 0x2000 /* 1 = parity of 32-bit buffer BD-bus*/
418 #define FM_STRPFCS 0x4000 /* 1 = strips FCS field of rec.frame */
419 #define FM_BMMODE 0x8000 /* Buffer-Memory-Mode (1 = tag mode) */
425 #define FM_STEFRMS 0x0001 /* transmit end of frame: synchr. qu.*/
426 #define FM_STEFRMA0 0x0002 /* transmit end of frame: asyn. qu.0 */
427 #define FM_STEFRMA1 0x0004 /* transmit end of frame: asyn. qu.1 */
428 #define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */
440 #define FM_STBFLA 0x0200 /* asynchr.-queue trans. buffer full */
441 #define FM_STBFLS 0x0400 /* synchr.-queue transm. buffer full */
442 #define FM_STXABRS 0x0800 /* synchr. queue transmit-abort */
443 #define FM_STXABRA0 0x1000 /* asynchr. queue 0 transmit-abort */
444 #define FM_STXABRA1 0x2000 /* asynchr. queue 1 transmit-abort */
445 #define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */
457 #define FM_STXINFLS 0x0010 /* transmit instruction full: syn. */
459 #define FM_STXINFLA0 0x0020 /* transmit instruction full: asyn.0 */
461 #define FM_STXINFLA1 0x0040 /* transmit instruction full: asyn.1 */
463 #define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */
486 #define FM_SERRSF 0x0080 /* error in special frame */
488 #define FM_SRFRCTOV 0x0200 /* receive frame counter overflow */
490 #define FM_SRCVFRM 0x0400 /* receive frame */
493 #define FM_SRBFL 0x1000 /* receive buffer full */
507 #define FM_SFRMCTR 0x0010 /* frame counter overflow */
512 #define FM_SMISFRM 0x0200 /* missed frame */
528 /* Bit 4-10: reserved */
530 #define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */
549 * MAC State-Machine Register FM_STMCHN
556 #define FM_SIM 0x1000 /* indicate send immediate-mode */
580 * Frame Selection Register
586 #define FM_RCV1_NSMT (3<<0) /* rec non-SMT frames */
597 #define FM_RCV2_NSMT (3<<4) /* rec non-SMT frames */
604 #define FM_ENXMTADSWAP 0x4000 /* enh rec addr swap (phys -> can) */
605 #define FM_ENRCVADSWAP 0x8000 /* enh tx addr swap (can -> phys) */
625 /* Bit 0-4: reserved */
633 #define FM_FULL 0x4000 /* CAM full */
654 * instruction set for command register 1 (NPADDR6-0 = 0x00)
669 #define FM_ISIM 0x0e /* enter send-immediate mode */
670 #define FM_IESIM 0x0f /* exit send-immediate mode */
678 #define FM_ITRXBUS 0x22 /* SN3: Tristate X-Bus (SAS only) */
679 #define FM_IDRXBUS 0x23 /* SN3: drive X-Bus */
683 * instruction set for command register 2 (NPADDR6-0 = 0x01)
696 #define FM_IERSF 0x40 /* enable receive single frame */
742 * Special Quad-Elm Registers.
743 * A Quad-ELM consists of for ELMs and these additional registers.
794 #define PL_MAINT 0x0004 /* if OFF state --> MAINT state */
796 #define PL_PC_JOIN 0x0010 /* if NEXT state --> JOIN state */
813 #define PL_M_TPDR (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/
827 * It contains the scrambling control registers (PLC-S only)
835 #define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */
872 #define PLC_REVISION_QA 0x0800 /* rev bits for ELM core in QELM-A */
876 #define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */
877 #define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */
921 #define PL_PC0 (0<<7) /* OFF - when /RST or PCM_CNTRL */
922 #define PL_PC1 (1<<7) /* BREAK - entry point in start PCM*/
923 #define PL_PC2 (2<<7) /* TRACE - to localize stuck Beacon*/
924 #define PL_PC3 (3<<7) /* CONNECT - synchronize ends of conn*/
925 #define PL_PC4 (4<<7) /* NEXT - to separate the signalng*/
926 #define PL_PC5 (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/
927 #define PL_PC6 (6<<7) /* JOIN - 1. state to activ conn. */
928 #define PL_PC7 (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */
929 #define PL_PC8 (8<<7) /* ACTIVE - PHY has been incorporated*/
930 #define PL_PC9 (9<<7) /* MAINT - for test purposes or so
953 #define PL_PARITY_ERR 0x0001 /* p. error h.b.detected on TX9-0 inp*/
962 #define PL_EBUF_ERR 0x0200 /* elastic buff. det. over-|underflow*/
1018 #define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */
1037 #define RQ_SFW 2 /* special frame write */