97 #define xemaclite_writel	iowrite32be  macro
100 #define xemaclite_writel	iowrite32  macro
156 	xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,  in xemaclite_enable_interrupts()
160 	xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);  in xemaclite_enable_interrupts()
163 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_enable_interrupts()
178 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);  in xemaclite_disable_interrupts()
182 	xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),  in xemaclite_disable_interrupts()
187 	xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),  in xemaclite_disable_interrupts()
346 	xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),  in xemaclite_send_data()
356 	xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);  in xemaclite_send_data()
449 	xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);  in xemaclite_recv_data()
476 	xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);  in xemaclite_update_address()
480 	xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);  in xemaclite_update_address()
658 		xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);  in xemaclite_interrupt()
668 		xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +  in xemaclite_interrupt()
734 	xemaclite_writel(XEL_MDIOADDR_OP_MASK |  in xemaclite_mdio_read()
737 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,  in xemaclite_mdio_read()
783 	xemaclite_writel(~XEL_MDIOADDR_OP_MASK &  in xemaclite_mdio_write()
786 	xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);  in xemaclite_mdio_write()
787 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,  in xemaclite_mdio_write()
843 	xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,  in xemaclite_mdio_setup()
1140 	xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);  in xemaclite_of_probe()
1141 	xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);  in xemaclite_of_probe()