Lines Matching refs:XEL_TSR_OFFSET
36 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ macro
155 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
157 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
181 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
183 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
321 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
334 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
354 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
356 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); in xemaclite_send_data()
479 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_update_address()
480 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); in xemaclite_update_address()
483 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & in xemaclite_update_address()
654 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); in xemaclite_interrupt()
658 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); in xemaclite_interrupt()
664 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); in xemaclite_interrupt()
669 XEL_TSR_OFFSET); in xemaclite_interrupt()
1140 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); in xemaclite_of_probe()
1141 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); in xemaclite_of_probe()