ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
33 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
36 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
107 #define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
108 #define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
122 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
128 #define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
129 #define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
146 #define XAE_TPF_OFFSET		0x00000004 /* Tx Pause Frame */
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
151 #define XAE_TTAG_OFFSET		0x00000018 /* Tx VLAN TAG */
157 #define XAE_PPST_OFFSET		0x00000030 /* PCS PMA Soft Temac Status Reg */
160 #define XAE_TC_OFFSET		0x00000408 /* Tx Configuration */
176 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
185 #define XAE_RAF_TXVTAGMODE_MASK		0x00000018 /* Tx VLAN TAG mode */
187 #define XAE_RAF_TXVSTRPMODE_MASK	0x00000180 /* Tx VLAN STRIP mode */
194 #define XAE_RAF_TXVTAGMODE_SHIFT	3 /* Tx Tag mode shift bits */
196 #define XAE_RAF_TXVSTRPMODE_SHIFT	7 /* Tx strip mode shift bits*/
200 #define XAE_TPF_TPFV_MASK		0x0000FFFF /* Tx pause frame value */
201 /* Transmit inter-frame gap adjustment value */
214 #define XAE_INT_TXCMPIT_MASK		0x00000020 /* Tx complete */
235 /* In-Band FCS enable (FCS not stripped) */
251 /* In-Band FCS enable (FCS not generated) */
255 /* Inter-frame gap adjustment enable */
260 #define XAE_FCC_FCTX_MASK	0x40000000 /* Tx flow control enable */
268 #define XAE_EMMC_TX16BIT	0x02000000 /* 16 bit Tx client enable */
277 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
343 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
348  * struct axidma_bd - Axi Dma buffer descriptor layout
373 	u32 app1;	/* TX start << 16 | insert */
374 	u32 app2;	/* TX csum seed */
383  * struct axienet_local - axienet private per device data
389  * @pcs_phy:	Reference to PCS/PMA PHY if used
390  * @pcs:	phylink pcs structure for PCS PHY
392  * @axi_clk:	AXI4-Lite bus clock
393  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
409  * @napi_tx:	NAPI TX control structure
410  * @tx_dma_cr:  Nominal content of TX DMA control register
411  * @tx_bd_v:	Virtual address of the TX buffer descriptor ring
412  * @tx_bd_p:	Physical address(start address) of the TX buffer descr. ring
413  * @tx_bd_num:	Size of TX buffer descriptor ring
414  * @tx_bd_ci:	Stores the next Tx buffer descriptor in the ring that may be
415  *		complete. Only updated at runtime by TX NAPI poll.
416  * @tx_bd_tail:	Stores the index of the next Tx buffer descriptor in the ring
418  * @tx_packets: TX packet count for statistics
419  * @tx_bytes:	TX byte count for statistics
420  * @tx_stat_sync: Synchronization object for TX stats
424  * @tx_irq:	Axidma TX IRQ number
427  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
435  * @csum_offload_on_tx_path:	Stores the checksum selection on TX side.
439  * @coalesce_count_tx:	Store the irq coalesce on TX side.
440  * @coalesce_usec_tx:	IRQ coalesce delay for TX
450 	struct phylink_pcs pcs;  member
509  * struct axiethernet_option - Used to set axi ethernet hardware options
521  * axienet_ior - Memory mapped Axi Ethernet register read
531 	return ioread32(lp->regs + offset);  in axienet_ior()
541 	if (lp->mii_bus)  in axienet_lock_mii()
542 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
547 	if (lp->mii_bus)  in axienet_unlock_mii()
548 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
552  * axienet_iow - Memory mapped Axi Ethernet register write
563 	iowrite32(value, lp->regs + offset);  in axienet_iow()
567  * axienet_dma_out32 - Memory mapped Axi DMA register write.
579 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
584  * axienet_dma_out64 - Memory mapped Axi DMA register write.
595 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
601 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()