ethernet/xilinx/xilinx_axienet.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Definitions for Xilinx Axi Ethernet device driver.
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
31 #define XAE_OPTION_PROMISC			(1 << 0)
34 #define XAE_OPTION_JUMBO			(1 << 1)
37 #define XAE_OPTION_VLAN				(1 << 2)
40 #define XAE_OPTION_FLOW_CONTROL			(1 << 4)
45 #define XAE_OPTION_FCS_STRIP			(1 << 5)
50 #define XAE_OPTION_FCS_INSERT			(1 << 6)
58 #define XAE_OPTION_LENTYPE_ERR			(1 << 7)
61 #define XAE_OPTION_TXEN				(1 << 11)
64 #define XAE_OPTION_RXEN				(1 << 12)
72 /* Axi DMA Register definitions */
125 #define XAXIDMA_DFT_RX_THRESHOLD	1
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
159 #define XAE_RCW1_OFFSET		0x00000404 /* Rx Configuration Word 1 */
170 #define XAE_UAW1_OFFSET		0x00000704 /* Unicast address word 1 */
174 #define XAE_AF1_OFFSET		0x00000714 /* Address Filter 1 */
180 /* Bit Masks for Axi Ethernet RAF register */
199 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
201 /* Transmit inter-frame gap adjustment value */
204 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
224 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
226 #define XAE_TPID_1_MASK		0xFFFF0000 /* TPID 1 */
228 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
230 #define XAE_TPID_3_MASK		0xFFFF0000 /* TPID 1 */
232 /* Bit masks for Axi Ethernet RCW1 register */
235 /* In-Band FCS enable (FCS not stripped) */
248 /* Bit masks for Axi Ethernet TC register */
251 /* In-Band FCS enable (FCS not generated) */
255 /* Inter-frame gap adjustment enable */
258 /* Bit masks for Axi Ethernet FCC register */
262 /* Bit masks for Axi Ethernet EMMC register */
274 /* Bit masks for Axi Ethernet PHYC register */
277 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
286 /* Bit masks for Axi Ethernet MDIO interface MC register */
290 /* Bit masks for Axi Ethernet MDIO interface MCR register */
302 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
305 /* Bit masks for Axi Ethernet UAW1 register */
311 /* Bit masks for Axi Ethernet FMC register */
317 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
319 #define XAE_PHY_TYPE_GMII		1
328 /* Axi Ethernet Synthesis features */
329 #define XAE_FEATURE_PARTIAL_RX_CSUM	(1 << 0)
330 #define XAE_FEATURE_PARTIAL_TX_CSUM	(1 << 1)
331 #define XAE_FEATURE_FULL_RX_CSUM	(1 << 2)
332 #define XAE_FEATURE_FULL_TX_CSUM	(1 << 3)
333 #define XAE_FEATURE_DMA_64BIT		(1 << 4)
348  * struct axidma_bd - Axi Dma buffer descriptor layout
358  * @app1:         MM2S/S2MM User Application Field 1.
365 	u32 next_msb;	/* high 32 bits for IP >= v7.1, reserved on older IP */
367 	u32 phys_msb;	/* for IP >= v7.1, reserved for older IP */
383  * struct axienet_local - axienet private per device data
392  * @axi_clk:	AXI4-Lite bus clock
393  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
421  * @dma_err_task: Work structure to process Axi DMA errors
427  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
430  * @max_frm_size: Stores the maximum size of the frame that can be that
509  * struct axiethernet_option - Used to set axi ethernet hardware options
521  * axienet_ior - Memory mapped Axi Ethernet register read
523  * @offset:     Address offset from the base address of Axi Ethernet core
525  * Return: The contents of the Axi Ethernet register
531 	return ioread32(lp->regs + offset);  in axienet_ior()
541 	if (lp->mii_bus)  in axienet_lock_mii()
542 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
547 	if (lp->mii_bus)  in axienet_unlock_mii()
548 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
552  * axienet_iow - Memory mapped Axi Ethernet register write
554  * @offset:     Address offset from the base address of Axi Ethernet core
555  * @value:      Value to be written into the Axi Ethernet register
557  * This function writes the desired value into the corresponding Axi Ethernet
563 	iowrite32(value, lp->regs + offset);  in axienet_iow()
567  * axienet_dma_out32 - Memory mapped Axi DMA register write.
569  * @reg:	Address offset from the base address of the Axi DMA core
570  * @value:	Value to be written into the Axi DMA register
572  * This function writes the desired value into the corresponding Axi DMA
579 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
584  * axienet_dma_out64 - Memory mapped Axi DMA register write.
586  * @reg:	Address offset from the base address of the Axi DMA core
587  * @value:	Value to be written into the Axi DMA register
589  * This function writes the desired value into the corresponding Axi DMA
595 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
601 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()