269 #define IOSYNC	do { ioread8(ioaddr + StationAddr); } while (0)
481 #define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
485 #define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
489 #define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
493 #define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
527 		bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask);  in rhine_wait_bit()
557 		intr_status |= ioread8(ioaddr + IntrStatus2) << 16;  in rhine_get_events()
582 		iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);  in rhine_power_init()
594 		wolstat = ioread8(ioaddr + PwrcsrSet);  in rhine_power_init()
596 			wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;  in rhine_power_init()
639 	if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {  in rhine_chip_reset()
650 	cmd1 = ioread8(ioaddr + ChipCmd1);  in rhine_chip_reset()
723 		iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);  in rhine_reload_eeprom()
835 			if (ioread8(ioaddr + ChipCmd) & CmdTxOn)  in rhine_napipoll()
937 		addr[i] = ioread8(ioaddr + StationAddr + i);  in rhine_init_one_common()
950 		phy_id = ioread8(ioaddr + 0x6C);  in rhine_init_one_common()
1356 	    iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,  in rhine_check_media()
1359 	    iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,  in rhine_check_media()
1858 	iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,  in rhine_start_tx()
2161 		iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,  in rhine_restart_tx()
2168 		iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,  in rhine_restart_tx()
2483 		iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);  in rhine_shutdown_pci()
2498 		iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);  in rhine_shutdown_pci()
2504 		iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);  in rhine_shutdown_pci()