Lines Matching refs:comm
16 void spl2sw_mac_hw_stop(struct spl2sw_common *comm) in spl2sw_mac_hw_stop() argument
20 if (comm->enable == 0) { in spl2sw_mac_hw_stop()
22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_mac_hw_stop()
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_mac_hw_stop()
26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
33 reg |= FIELD_PREP(MAC_DIS_PORT, ~comm->enable); in spl2sw_mac_hw_stop()
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
37 void spl2sw_mac_hw_start(struct spl2sw_common *comm) in spl2sw_mac_hw_start() argument
42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
49 reg &= FIELD_PREP(MAC_DIS_PORT, ~comm->enable) | ~MAC_DIS_PORT; in spl2sw_mac_hw_start()
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
55 struct spl2sw_common *comm = mac->comm; in spl2sw_mac_addr_add() local
61 comm->l2sw_reg_base + L2SW_W_MAC_15_0); in spl2sw_mac_addr_add()
64 comm->l2sw_reg_base + L2SW_W_MAC_47_16); in spl2sw_mac_addr_add()
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_add()
73 comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_add()
80 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_add()
82 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)), in spl2sw_mac_addr_add()
84 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0))); in spl2sw_mac_addr_add()
90 struct spl2sw_common *comm = mac->comm; in spl2sw_mac_addr_del() local
96 comm->l2sw_reg_base + L2SW_W_MAC_15_0); in spl2sw_mac_addr_del()
99 comm->l2sw_reg_base + L2SW_W_MAC_47_16); in spl2sw_mac_addr_del()
105 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_del()
109 comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_del()
116 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), in spl2sw_mac_addr_del()
118 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)), in spl2sw_mac_addr_del()
120 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0))); in spl2sw_mac_addr_del()
124 void spl2sw_mac_hw_init(struct spl2sw_common *comm) in spl2sw_mac_hw_init() argument
129 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
131 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
134 writel(comm->desc_dma, comm->l2sw_reg_base + L2SW_TX_LBASE_ADDR_0); in spl2sw_mac_hw_init()
135 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * TX_DESC_NUM, in spl2sw_mac_hw_init()
136 comm->l2sw_reg_base + L2SW_TX_HBASE_ADDR_0); in spl2sw_mac_hw_init()
137 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM + in spl2sw_mac_hw_init()
138 MAC_GUARD_DESC_NUM), comm->l2sw_reg_base + L2SW_RX_HBASE_ADDR_0); in spl2sw_mac_hw_init()
139 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM + in spl2sw_mac_hw_init()
141 comm->l2sw_reg_base + L2SW_RX_LBASE_ADDR_0); in spl2sw_mac_hw_init()
144 writel(0x4a3a2d1d, comm->l2sw_reg_base + L2SW_FL_CNTL_TH); in spl2sw_mac_hw_init()
147 writel(0x4a3a1212, comm->l2sw_reg_base + L2SW_CPU_FL_CNTL_TH); in spl2sw_mac_hw_init()
150 writel(0xf6680000, comm->l2sw_reg_base + L2SW_PRI_FL_CNTL); in spl2sw_mac_hw_init()
153 reg = readl(comm->l2sw_reg_base + L2SW_LED_PORT0); in spl2sw_mac_hw_init()
155 writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0); in spl2sw_mac_hw_init()
161 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
166 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_init()
172 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_init()
176 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_init()
179 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL1); in spl2sw_mac_hw_init()
181 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL1); in spl2sw_mac_hw_init()
186 reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mac_hw_init()
190 writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE); in spl2sw_mac_hw_init()
196 writel(reg, comm->l2sw_reg_base + L2SW_PVID_CONFIG0); in spl2sw_mac_hw_init()
202 writel(reg, comm->l2sw_reg_base + L2SW_VLAN_MEMSET_CONFIG0); in spl2sw_mac_hw_init()
208 reg = readl(comm->l2sw_reg_base + L2SW_SW_GLB_CNTL); in spl2sw_mac_hw_init()
213 writel(reg, comm->l2sw_reg_base + L2SW_SW_GLB_CNTL); in spl2sw_mac_hw_init()
215 writel(MAC_INT_MASK_DEF, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_mac_hw_init()
220 struct spl2sw_common *comm = mac->comm; in spl2sw_mac_rx_mode_set() local
227 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_rx_mode_set()
242 writel((reg & (~mask)) | ((~rx_mode) & mask), comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_rx_mode_set()
243 netdev_dbg(ndev, "cpu_cntl = %08x\n", readl(comm->l2sw_reg_base + L2SW_CPU_CNTL)); in spl2sw_mac_rx_mode_set()
246 void spl2sw_mac_init(struct spl2sw_common *comm) in spl2sw_mac_init() argument
251 comm->rx_pos[i] = 0; in spl2sw_mac_init()
254 spl2sw_mac_hw_init(comm); in spl2sw_mac_init()
257 void spl2sw_mac_soft_reset(struct spl2sw_common *comm) in spl2sw_mac_soft_reset() argument
261 spl2sw_mac_hw_stop(comm); in spl2sw_mac_soft_reset()
263 spl2sw_rx_descs_flush(comm); in spl2sw_mac_soft_reset()
264 comm->tx_pos = 0; in spl2sw_mac_soft_reset()
265 comm->tx_done_pos = 0; in spl2sw_mac_soft_reset()
266 comm->tx_desc_full = 0; in spl2sw_mac_soft_reset()
269 comm->rx_pos[i] = 0; in spl2sw_mac_soft_reset()
272 spl2sw_mac_hw_init(comm); in spl2sw_mac_soft_reset()
273 spl2sw_mac_hw_start(comm); in spl2sw_mac_soft_reset()