Lines Matching full:receive

18 #define DMA_RCV_BASE_ADDR	0x0000100c	/* Receive List Base */
70 #define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */
76 #define DMA_INTR_ENA_RIE 0x00000040	/* Receive Interrupt */
77 #define DMA_INTR_ENA_ERE 0x00004000	/* Early Receive */
86 #define DMA_INTR_ENA_RWE 0x00000200	/* Receive Watchdog */
87 #define DMA_INTR_ENA_RSE 0x00000100	/* Receive Stopped */
88 #define DMA_INTR_ENA_RUE 0x00000080	/* Receive Buffer Unavailable */
90 #define DMA_INTR_ENA_OVE 0x00000010	/* Receive Overflow */
112 #define DMA_STATUS_RS_MASK	0x000e0000	/* Receive Process State */
116 #define DMA_STATUS_ERI	0x00004000	/* Early Receive Interrupt */
119 #define DMA_STATUS_RWT	0x00000200	/* Receive Watchdog Timeout */
120 #define DMA_STATUS_RPS	0x00000100	/* Receive Process Stopped */
121 #define DMA_STATUS_RU	0x00000080	/* Receive Buffer Unavailable */
122 #define DMA_STATUS_RI	0x00000040	/* Receive Interrupt */
124 #define DMA_STATUS_OVF	0x00000010	/* Receive Overflow */