21 static void dwmac5_log_error(struct net_device *ndev, u32 value, bool corr,  in dwmac5_log_error()  argument
31 	mask = value;  in dwmac5_log_error()
81 	u32 value;  in dwmac5_handle_mac_err()  local
83 	value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);  in dwmac5_handle_mac_err()
84 	writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);  in dwmac5_handle_mac_err()
86 	dwmac5_log_error(ndev, value, correctable, "MAC", dwmac5_mac_errors,  in dwmac5_handle_mac_err()
129 	u32 value;  in dwmac5_handle_mtl_err()  local
131 	value = readl(ioaddr + MTL_ECC_INT_STATUS);  in dwmac5_handle_mtl_err()
132 	writel(value, ioaddr + MTL_ECC_INT_STATUS);  in dwmac5_handle_mtl_err()
134 	dwmac5_log_error(ndev, value, correctable, "MTL", dwmac5_mtl_errors,  in dwmac5_handle_mtl_err()
177 	u32 value;  in dwmac5_handle_dma_err()  local
179 	value = readl(ioaddr + DMA_ECC_INT_STATUS);  in dwmac5_handle_dma_err()
180 	writel(value, ioaddr + DMA_ECC_INT_STATUS);  in dwmac5_handle_dma_err()
182 	dwmac5_log_error(ndev, value, correctable, "DMA", dwmac5_dma_errors,  in dwmac5_handle_dma_err()
200 	u32 value;  in dwmac5_safety_feat_config()  local
209 	value = readl(ioaddr + MTL_ECC_CONTROL);  in dwmac5_safety_feat_config()
210 	value |= MEEAO; /* MTL ECC Error Addr Status Override */  in dwmac5_safety_feat_config()
212 		value |= TSOEE; /* TSO ECC */  in dwmac5_safety_feat_config()
214 		value |= MRXPEE; /* MTL RX Parser ECC */  in dwmac5_safety_feat_config()
216 		value |= MESTEE; /* MTL EST ECC */  in dwmac5_safety_feat_config()
218 		value |= MRXEE; /* MTL RX FIFO ECC */  in dwmac5_safety_feat_config()
220 		value |= MTXEE; /* MTL TX FIFO ECC */  in dwmac5_safety_feat_config()
221 	writel(value, ioaddr + MTL_ECC_CONTROL);  in dwmac5_safety_feat_config()
224 	value = readl(ioaddr + MTL_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
225 	value |= RPCEIE; /* RX Parser Memory Correctable Error */  in dwmac5_safety_feat_config()
226 	value |= ECEIE; /* EST Memory Correctable Error */  in dwmac5_safety_feat_config()
227 	value |= RXCEIE; /* RX Memory Correctable Error */  in dwmac5_safety_feat_config()
228 	value |= TXCEIE; /* TX Memory Correctable Error */  in dwmac5_safety_feat_config()
229 	writel(value, ioaddr + MTL_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
232 	value = readl(ioaddr + DMA_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
233 	value |= TCEIE; /* TSO Memory Correctable Error */  in dwmac5_safety_feat_config()
234 	writel(value, ioaddr + DMA_ECC_INT_ENABLE);  in dwmac5_safety_feat_config()
241 	value = readl(ioaddr + MAC_FSM_CONTROL);  in dwmac5_safety_feat_config()
243 		value |= PRTYEN; /* FSM Parity Feature */  in dwmac5_safety_feat_config()
245 		value |= TMOUTEN; /* FSM Timeout Feature */  in dwmac5_safety_feat_config()
246 	writel(value, ioaddr + MAC_FSM_CONTROL);  in dwmac5_safety_feat_config()
249 	value = readl(ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
251 		value |= EDPP;  in dwmac5_safety_feat_config()
252 	writel(value, ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
262 		value |= EPSI;  in dwmac5_safety_feat_config()
263 	writel(value, ioaddr + MTL_DPP_CONTROL);  in dwmac5_safety_feat_config()
639 	u32 status, value, feqn, hbfq, hbfs, btrl;  in dwmac5_est_irq_status()  local
644 	value = (CGCE | HLBS | HLBF | BTRE | SWLC);  in dwmac5_est_irq_status()
647 	if (!(status & value))  in dwmac5_est_irq_status()
658 		value = readl(ioaddr + MTL_EST_SCH_ERR);  in dwmac5_est_irq_status()
659 		value &= txqcnt_mask;  in dwmac5_est_irq_status()
664 		writel(value, ioaddr + MTL_EST_SCH_ERR);  in dwmac5_est_irq_status()
671 			netdev_err(dev, "EST: HLB(sched) Queue 0x%x\n", value);  in dwmac5_est_irq_status()
675 		value = readl(ioaddr + MTL_EST_FRM_SZ_ERR);  in dwmac5_est_irq_status()
676 		feqn = value & txqcnt_mask;  in dwmac5_est_irq_status()
678 		value = readl(ioaddr + MTL_EST_FRM_SZ_CAP);  in dwmac5_est_irq_status()
679 		hbfq = (value & SZ_CAP_HBFQ_MASK(txqcnt)) >> SZ_CAP_HBFQ_SHIFT;  in dwmac5_est_irq_status()
680 		hbfs = value & SZ_CAP_HBFS_MASK;  in dwmac5_est_irq_status()
717 	u32 value;  in dwmac5_fpe_configure()  local
721 		value = readl(ioaddr + GMAC_RXQ_CTRL1);  in dwmac5_fpe_configure()
722 		value &= ~GMAC_RXQCTRL_FPRQ;  in dwmac5_fpe_configure()
723 		value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;  in dwmac5_fpe_configure()
724 		writel(value, ioaddr + GMAC_RXQ_CTRL1);  in dwmac5_fpe_configure()
733 	u32 value;  in dwmac5_fpe_irq_status()  local
741 	value = readl(ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_irq_status()
743 	if (value & TRSP) {  in dwmac5_fpe_irq_status()
748 	if (value & TVER) {  in dwmac5_fpe_irq_status()
753 	if (value & RRSP) {  in dwmac5_fpe_irq_status()
758 	if (value & RVER) {  in dwmac5_fpe_irq_status()
769 	u32 value = cfg->fpe_csr;  in dwmac5_fpe_send_mpacket()  local
772 		value |= SVER;  in dwmac5_fpe_send_mpacket()
774 		value |= SRSP;  in dwmac5_fpe_send_mpacket()
776 	writel(value, ioaddr + MAC_FPE_CTRL_STS);  in dwmac5_fpe_send_mpacket()